How to change the GPU frequency

Applicable for

STM32MP23x lines, STM32MP25x lines

---

Trusted domain applicability

This article is only applicable to A35-TD flavor of STM32MP2 series

1. Purpose

This article explains how to change the GPU operating point (also known as OPP). An operating point corresponds to the frequency of the processor and the voltage that needs to be supplied to sustain it.

2. Hardware side

On STM32MP23x lines  and STM32MP25x lines  products, the GPU sub-system:

• is clocked by PLL3 from the RCC internal peripheral in OpenSTLinux
• is supplied with V_DDGPU voltage provided by a PWR regulator

The part number tells the device maximum supported frequency with associated usage conditions:

• for STM32MP23
  • up to 400 MHz, the nominal frequency
• for STM32MP25
  • up to 800 MHz, the nominal frequency with nominal V_DDGPU at 0.8V
  • only for part numbers with overdrive support, the overdrive frequency is 900 MHz with V_DDGPU at 0.9V
    refer to the AN5729 document for impact of this overdrive GPU OPP on STM32MP25 life time usage.

3. Software side

In OpenSTLinux distribution, OP-TEE sets the GPU configuration used when the GPU sub-system, with associated SCMI power domain, is activated; that is the maximum frequency sustainable with the supported voltage and with a supported PLL3 configuration.

3.1. DT configuration (STM32/SoC level)

The GPU sub-system configuration is defined in the OP-TEE "soc" device tree file:

• core/arch/arm/dts/stm32mp235.dtsi
• core/arch/arm/dts/stm32mp255.dtsi

The GPU node references the used clock, supply and OPP table. The OPP table contains one or several frequency / voltage pair(s).

Warning

This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

3.1.1. GPU node

&rifsc {
	gpu: gpu@48280000 {
		compatible = "vivante,gc";
		gpu-supply = <&vddgpu>;
		clocks = <&rcc CK_KER_GPU>;
		operating-points-v2 = <&gpu_opp_table>;
		access-controllers = <&rifsc STM32MP25_RIFSC_GPU_ID>;
	};
};

3.1.2. OPP table

• OPP table for STM32MP23x lines :

/ {
	gpu_opp_table: opp-table-gpu {
		compatible = "operating-points-v2";

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <800000>;
			opp-supported-hw = <0x3>;
			st,opp-default;
		};
	};
};

• OPP table for STM32MP25x lines :

/ {
	gpu_opp_table: opp-table-gpu {
		compatible = "operating-points-v2";

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <800000>;
			opp-supported-hw = <0x3>;
			st,opp-default;
		};

		opp-900000000 {
			opp-hz = /bits/ 64 <900000000>;
			opp-microvolt = <900000>;
			opp-supported-hw = <0x2>;
		};
	};
};

The operating points are defined with the associated bit-field opp-supported-hw

• bit 0: supported by part number = STM32MP2xxA / STM32MP2xxC
• bit 1: supported by part number = STM32MP2xxD / STM32MP2xxF (overdrive support)

Notes:

• OP-TEE selects the highest st,opp-default supported OPP during the GPU activation.

3.2. DT configuration (board level)

The objective of this chapter is to explain how to change GPU system configuration, including supply and clock, for a given board.

This configuration should be done in specific board device tree files (board dts file).

3.2.1. V_DDGPU voltage configuration

The external voltage V_DDGPU is provided to the PWR internal peripheral, indicated in pwr node by the vddgpu-supply property in the vddgpu sub-node.

You can reduce the list of supported V_DDGPU voltage for your board, for example when fixed or gpio regulator is used, the OPP GPU driver in OP-TEE will automatically skip the OPP for unsupported voltage.

Information

On STMicroelectronic boards, this voltage is provided by a STPMIC regulator with a range of supported voltage. Read PMIC article for device tree configuration.

The example below sets STPMIC25 BUCK3 minimal voltage to 0.8 V and max to 0.9V, allowing to provided the expected nominal and overdrive voltage on PWR V_DDGPU for the GPU on STM32MP25 board:

&pwr {
   ...
	vddgpu: vddgpu {
		status = "okay";
		vddgpu-supply = <&vddgpu_pmic>;
	};
};
...
pmic2: stpmic2@33 {
	vddgpu_pmic: buck3 {
		regulator-name = "vddgpu_pmic";
		regulator-min-microvolt = <800000>;
		regulator-max-microvolt = <900000>;
		regulator-over-current-protection;
	};
};

3.2.2. PLL3 configuration

The PLL3 configurations needed to reach the above frequencies must be described via the st,ck_gpu, st,pll-3 and property in rcc device tree node on OP-TEE device tree.

See Clock device tree configuration for binding details.

For example in core/arch/arm/dts/stm32mp257f-dk-ca35tdcid-rcc.dtsi , generated by STM32MP2 clock tree:

	pll3: st,pll-3 {
		st,pll = <&pll3_cfg_800Mhz>;

		pll3_cfg_800Mhz: pll3-cfg-800Mhz {
			cfg = <20 1 1 1>;
			src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
		};

		pll3_cfg_900Mhz: pll3-cfg-900Mhz {
			cfg = <45 2 1 1>;
			src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
		};
	};

And in core/arch/arm/dts/stm32mp257f-dk.dts :

&rcc {
	st,clk_opp {
...
		st,ck_gpu {
			cfg_1 {
				hz = <800000000>;
				st,pll = <&pll3_cfg_800Mhz>;
			};

			cfg_2 {
				hz = <900000000>;
				st,pll = <&pll3_cfg_900Mhz>;
			};
		};
	};
};

You can reduce the list of supported PLL3 configuration for your board, the OPP GPU driver in OP-TEE will automatically skip the OPP for unsupported PLL3 frequency.

3.3. GPU OPP selection

3.3.1. Default GPU OPP at boot

OP-TEE selects the nominal GPU OPP at boot identified with st,opp-default in the SOC device tree.

For ecosystem release ≥ v6.2.0 the GPU OPP can be selected in Linux, so this default OPP should be not changed in OP-TEE board device tree.

For ecosystem release v6.1.0

For ecosystem release ≤ v6.1.0 , the GPU OPP can be only selected at boot.

To select by default the overdrive GPU OPP on STM32MP25, in your OP-TEE board device tree file, you indicate that the overdrive OPP opp-900000000 is sustainable with st,opp-default:

&opp-table-gpu {
		opp-900000000 {
			st,opp-default;
		};
};

Warning

Refer to the AN5729 document for impact on life time usage of this overdrive GPU OPP with VDDGPU at 0.9V.

For ecosystem release v6.0.0

On ecosystem release v6.0.0 , the GPU OPP driver doesn't yet correctly manage the GPU clock and supply associated to GPU OPP, so you must force:

• the selected PLL3 configuration with st,pll property
• the V_DDGPU supply value to respect the targeted GPU OPP.

For example to use overdrive frequency at 900MHz for GPU activation, you must change the initial configuration:

	pll3: st,pll-3 {
		st,pll = <&pll3_cfg_800Mhz>;

		pll3_cfg_800Mhz: pll3-cfg-800Mhz {
			cfg = <20 1 1 1>;
			src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
		};

		pll3_cfg_900Mhz: pll3-cfg-900Mhz {
			cfg = <45 2 1 1>;
			src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
		};
	};

to

	pll3: st,pll-3 {
		st,pll = <&pll3_cfg_900Mhz>;
...
	};

And also force the minimal V_DDGPU voltage with:

&vddgpu_pmic {
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;
};

With the default OPP configuration:

&opp-table-gpu {
		opp-900000000 {
			st,opp-default;
		};
};

Warning

Refer to the AN5729 document for impact on life time usage of this overdrive GPU OPP with VDDGPU at 0.9V.

3.3.2. GPU OPP selection in Linux

As described in #DT configuration (STM32/SoC level) chapter, OPPs are fully described (frequencies, voltages, default...) in OP-TEE device trees.

In ecosystem release ≥ v6.2.0 they are exposed to Linux with SCMI and it is possible to dynamically change the GPU OPPs on STM32MP25 with a perf GPU power domain and the associated devfreq device.

In Linux kernel device trees, SOC dtsi file for the part number with several OPPs have power-domain starting with <&scmi_perf 1> and power-domain-names starting with "perf".

See the example arch/arm64/boot/dts/st/stm32mp255.dtsi :

	gpu: gpu@48280000 {
		compatible = "vivante,gc";
		reg = <0x48280000 0x800>;
		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&rcc GPU_R>;
		clock-names = "bus", "core";
		clocks = <&rcc CK_BUS_GPU>, <&rcc CK_KER_GPU>;
		power-domains =<&scmi_perf 1>, <&scmi_devpd PD_SCMI_GPU>, <&d1_pd>;
		power-domain-names = "perf", "scmi_devpd", "d1_pd";
		access-controllers = <&rifsc 79>;
		status = "disabled";

		throttle,max_state = <6>;
		#cooling-cells = <2>;
	};

In the userland, when the GPU is NOT running, it is possible to switch between OPPs and to check current OPP using following commands:

# Switch GPU OPP to 900MHz
echo 900000000 > /sys/class/devfreq/genpd:0:48280000.gpu/userspace/set_freq
# Switch GPU OPP to 800MHz
echo 800000000 > /sys/class/devfreq/genpd:0:48280000.gpu/userspace/set_freq

# Get state information related to GPU OPPs
cd /sys/class/devfreq/genpd:0:48280000.gpu
cat available_frequencies
cat trans_stat

# Get Debug information related to pm, regulators and clks
cat /sys/kernel/debug/devfreq/devfreq_summary
cat /sys/kernel/debug/pm_genpd/pm_genpd_summary | grep gpu
cat /sys/kernel/debug/regulator/regulator_summary | grep gpu
cat /sys/kernel/debug/clk/clk_summary | grep gpu
cat /sys/kernel/debug/clk/stm32_clk_summary | grep -1 gpu

Warning

Refer to the AN5729 document for impact on life time usage of this overdrive GPU OPP for STM32MP25 with VDDGPU at 0.9V.

4. How to go further

• Clock device tree configuration (looks for "how to build a clock tree" according to your product)

Arm^® Cortex^®-A35 trusted domain

Operating performance point (link to voltage and frequency scaling)

Graphics processing units

Device tree

Open portable trusted execution environment

Resource isolation framework Security Controller - NEW

High speed external oscillator (STM32 clock source)

Linux^® is a registered trademark of Linus Torvalds.

Generic interrupt controller

Serial peripheral interface

System control and management interface

Arm^® Cortex^®-A35 trusted domain

Operating performance point (link to voltage and frequency scaling)

Graphics processing units

Device tree

Open portable trusted execution environment

Resource isolation framework Security Controller - NEW

High speed external oscillator (STM32 clock source)

Linux^® is a registered trademark of Linus Torvalds.

Generic interrupt controller

Serial peripheral interface

System control and management interface

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®