1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the SAES peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The SAES peripheral provides hardware acceleration to encrypt or decrypt data using the AES[1] algorithms. It supports two key sizes (128 bits and 256 bits) and different chaining modes. It incorporates protections against differential power analysis (DPA) and the related side-channel attacks.
The SAES peripheral is connected to HUK and BHK over dedicated hardware busses that allows to wrap/unwrap keys based on specific protected hardware keys.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
The SAES instance is used to decrypt the loaded firmware when device is in secured locked state.
3.1.1. On STM32MP13x lines
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Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
Security | SAES | SAES | ☐ | ☑ | ROM code allocation is managed with the bit 7 in OTP 9 |
3.1.2. On STM32MP21x lines
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Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Security | SAES | SAES | ☐ | ☑ | ⬚ | ROM code allocation is managed with the bit 8 in OTP 16 |
3.1.3. On STM32MP23x lines
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Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Security | SAES | SAES | ☐ | ☑ | ⬚ | ROM code allocation is managed with the bit 8 in OTP 16 |
3.1.4. On STM32MP25x lines
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Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Security | SAES | SAES | ☐ | ☑ | ⬚ | ROM code allocation is managed with the bit 8 in OTP 16 |
3.2. Runtime assignment[edit | edit source]
3.2.1. On STM32MP13x lines
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Domain | Peripheral | Runtime allocation | Comment ![]() | ||
---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
Security | SAES | SAES | ☐ | ⬚ | Assignment (single choice) |
3.2.2. On STM32MP21x lines
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Domain | Peripheral | Runtime allocation | Comment ![]() | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Security | SAES | SAES | ☐OP-TEE | ⬚ | ☐ | ⬚ |
3.2.3. On STM32MP23x lines
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Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Security | SAES | SAES | ☐OP-TEE | ⬚ | ☐ | ⬚ |
3.2.4. On STM32MP25x lines
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Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | |||||
---|---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
Security | SAES | SAES | ☐OP-TEE | ⬚ | ☐ | ⬚ |
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers managing the SAES peripheral for the embedded software components listed in the above tables.
- Linux®: crypto framework
- OP-TEE: SAES driver, Cryptographic Provider API (CP API) and HUK support
- TF-A BL2: SAES driver
5. How to assign and configure the peripheral[edit | edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
6. References[edit | edit source]