STM32MP15 ecosystem errata sheet
The STM32MP15xx device errata document lists the different device errata and explains the associated workaround (software and/or hardware) if any.
Among those STM32MP15xx device errata, this article aims to describe which workarounds are implemented in STM32MP15 ecosystem releases.
Here is the legend for the column "Status STM32MP15xx Rev.B" in the table below, which refers to the availability of a workaround for the described errata:
- A = workaround available
- P = partial workaround available
Here is the legend for the column "STM32MP15-Ecosystem-vx.x.x Status" in the table below, which refers to the availability of a workaround in the given STM32MP15 ecosystem release:
- I = workaround Implemented
- P = workaround Partialy implemented
- N= workaround Not implemented
- NA= workaround Not Applicable
Fly over the letters in the table to show the legend locally.
ecosystem release v1.0.0
ecosystem release v1.1.0
|Comment about the workaround implemented in STM32MP15 ecosystem|
|Arm® Cortex®-A7 core||2.1.1||Memory locations might be accessed speculatively due to instruction fetches when HCR.VM is set||A||N||N||Workaround not implemented: STM32MPU Embedded Software distribution does not activate Cortex®-A7 hypervisor mode and so Virtual Memory second stage of translation.|
It is customer responsibility to implement the workaround if hypervisor mode used in its product.
|2.1.2||Cache maintenance by set/way operations can execute out of order||A||N||N||Limited impact on system. Implementation accepted by the community since Linux kernel v5.3 in arch/arm/Kconfig (look for ARM_ERRATA_814220) so it can already be backported, if needed.|
|2.1.4||PMU event counter 0x14 does not increment correctly||A||N||N||No impact on system. Minor impact performance measurement.|
No workaround provided by Arm for Linux kernel PMU driver.
|Arm® Cortex®-M4 core||2.2.1||Interrupted loads to SP can cause erroneous behavior||A||N||N||Limitation only on hand-written assembly code.|
Customer to implement workaround in its product assembly code.
|2.2.2||VDIV or VSQRT instructions might not complete correctly when very short ISRs are used||A||N||N||STM32CubeMP1 Package provided as example.|
It is customer responsibility to implement one of the proposed workarounds according to its user code and product configuration.
|2.2.3||Store immediate overlapping exception return operation might vector to incorrect interrupt||A||N||N||Impact on system is minor.|
Workaround to be implemented by customer according to its MPU configuration.
|System||2.3.1||TPIU fails to output sync after the pattern generator is disabled in Normal mode||A||N||N||No workaround implemented.|
No impact on system, issue happens only trace port.
|2.3.3||HSE external oscillator required in some LTDC use cases||P||I||I||HW implementation of external oscillator connected to the HSE pins available on STM32MP157C-EV1 MB1263 Rev.C (aka "MB1263C") and STM32MP157X-DKX MB1272 Rev.C (aka "MB1272C")|
|2.3.4||RCC cannot exit Stop and LP-Stop modes||A||I||I||Implemented in TF-A plat/st/stm32mp1/bl2_plat_setup.c|
|2.3.5||Incorrect reset of glitch-free kernel clock switch||P||I||I||STPMIC1 performs a VDDCORE reset on NRST activation, by default|
|2.3.6||Limitation of aclk/hclk5/hclk6 to 200 MHz when used as SDMMC1/2 kernel clock||P||I||I||Implemented in TF-A fdts with a clock tree that uses a SDMMC1/SDMMC2 kernel clock source that is not the aclk/hclk5/hclk6 bus clock|
|2.3.8||eMMC boot timeout too short||A||I||I||Implemented in STM32MP157C-EV1 MB1263 Rev.C (aka "MB1263C") that uses an eMMC that meets the required timing.|
|2.3.9||Cortex-M4 cannot use I/O compensation on Standby mode exit||A||I||I||The examples delivered with STM32Cube only use IOSPEEDR[1:0] settings 00 and 01.|
|DDRPHYC||2.4.1||DDRPHYC overconsumption upon reset or Standby mode exit||A||P||P||DDRPHYC is correctly reinitialized by TF-A after reset and Standby mode exit.|
Issue remains in case of Cortex®-M4 standalone wake-up as TF-A not executed and so DDRPHYC not reinitialized in such case.
|2.4.2||DDR_CLK jitter out of JEDEC requirement for 32-bit LPDDR2/LPDDR3 at low device Tj||A||NA||NA||ST boards are using DDR3, not LpDDR2/3.|
|2.4.3||Data corruption at low device Tj combined with low 32-bit LPDDR2/LPDDR3 I/O supply voltage||A||NA||NA||ST boards are using DDR3, not LpDDR2/3.|
|DMAMUX||2.5.4||Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event||A||P||P||Not applicable in OpenSTLinux distribution as DMA synchronous mode not used. |
|QUADSPI||2.6.1||Memory-mapped read of last memory byte fails||P||A||A||Implemented in OpenSTLinux distribution drivers/spi/spi-stm32-qspi.c|
|ADC||2.7.1||ADC ANA0/ANA1 resolution limited when Gigabit Ethernet is used||P||P||P||Customer should implement workaround by limiting ADC data resolution in OpenSTLinux distribution device tree configuration or in its STM32CubeMP1 Package based application.|
|2.7.2||ADC missing codes in differential 16-bit static acquisition||P||P||P||Customer should implement workaround by limiting ADC data resolution in OpenSTLinux distribution device tree configuration or in its STM32CubeMP1 Package based application.|
|DAC||2.8.1||Invalid DAC channel analog output if the DAC channel MODE bitfield is programmed before
|A||P||P||Linux DAC driver only uses the normal mode and never needs to change the MODE bitfield.|
All modes (normal, sample & hold) are supported by the HAL. It is up to the user to properly call HAL_DAC_Init before HAL_DAC_ConfigChannel to avoid the issue.
|DTS||2.9.1||Mode using PCLK & LSE (REFCLK_SEL = 1) should not be used||P||I||I||Implemented in OpenSTLinux distribution drivers/thermal/st/stm_thermal.c|
|TIM||2.11.1||One-pulse mode trigger not detected in master-slave reset + trigger configuration||P||N||N||Proposed workaround is only a recommendation|
|LPTIM||2.12.1||MCU may remain stuck in LPTIM interrupt when entering Stop mode||A||N||N||Interrupt not used in OpenSTLinux distribution. |
Workaround not implemented in STM32CubeMP1 Package. It is customer responsibility to implement it in MspDeinit().
|2.12.2||MCU may remain stuck in LPTIM interrupt when clearing event flag||P||I||I||Interrupt not used in OpenSTLinux distribution. |
|RTC and TAMP||2.13.2||Calendar initialization may fail in case of consecutive INIT mode entry||A||I||I||Implemented in OpenSTLinux distribution drivers/rtc/rtc-stm32.c|
|I2C||2.14.1||Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period||P||I||I||Implemented in TF-A fdts with a clock tree configuring I2C kernel clock source greater than 20MHz.|
|2.14.2||Spurious bus error detection in master mode||A||N||N||Workaround not implemented, neither in OpenSTLinux distribution nor within STM32CubeMP1 Package, in order to properly get real bus error notifications.|
|2.14.3||Spurious master transfer upon own slave address match||P||NA||NA||Multi-mastering mode implementation of STM32CubeMP1 Package I2C HAL driver prevents to enter in such case.|
|2.14.5||Transmission stalled after first byte transfer||A||N||N|
|SPI||2.15.1||Master data transfer stall at system clock much faster than SCK||A||I||I||SPI is disabled after each EOT in OpenSTLinux distribution drivers/spi/spi-stm32.c and in STM32CubeMP1 Package Src/stm32mp1xx_hal_spi.c .|
|2.15.2||Corrupted CRC return at non-zero UDRDET setting||P||N||N||Slave mode & CRC not supported in OpenSTLinux distribution. |
Not implemented in STM32CubeMP1 Package.
|2.15.3||TXP interrupt occurring while SPI disabled||A||I||I||Implemented in OpenSTLinux distribution, drivers/spi/spi-stm32.c ensures that all interrupts are disabled before the SPI is disabled.|
|2.15.4||Possible corruption of last-received data depending on CRCSIZE setting||A||N||N||CRC not supported in OpenSTLinux distribution.|
|FDCAN||2.16.1||Desynchronization under specific condition with edge filtering enabled||A||N||N|
|2.16.2||Tx FIFO messages inverted under specific buffer usage and priority setting||A||N||N|
|2.16.3||DAR mode transmission failure due to lost arbitration||A||N||N|
|ETH||2.17.2||Rx DMA may fail to recover upon DMA restart following a bus error, with Rx timestamping enabled||A||N||N|
|2.17.3||Tx DMA may halt while fetching TSO header under specific conditions||A||N||N|
|2.17.4||Spurious receive watchdog timeout interrupt||A||N||N|
|2.17.5||Incorrect flexible PPS output interval under specific conditions||A||N||N|
|2.17.6||Packets dropped in RMII 10Mbps mode due to fake dribble and CRC error||A||N||N|
|2.17.7||ARP offload function not effective||A||P||P||Customer to activate ARP software support in OpenSTLinux distribution.|
Power Management Unit (in STPMIC context) or Performance Monitoring Unit (in Arm Cortex-A context)
also known as
Low Power (MIPI® Alliance DSI standard)
former spelling for e•MMC ('e' in italic)
Trusted Firmware for Arm Cortex-A
Doubledata rate (memory domain)
Direct Memory Access
Hardware Abstraction Layer
Analog-to-digital converter. The process of converting a sampled analog signal to a digital code that represents the amplitude of the original signal sample.
low-power timer (STM32 specific)
Serial Peripheral Interface
End Of Transmission (MIPI® Alliance DSI standard)
Cyclic redundancy check calculation unit
Protocol used by the Internet Protocol, specifically IPv4, to map IP network addresses to the hardware addresses used by a data link protocol (https://en.wikipedia.org/wiki/Address_Resolution_Protocol)