1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the USB3DR peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The USB3DR peripheral is used to interconnect other systems with STM32 MPU devices using USB standard. The USB3DR peripheral is a USB Dual-Role Device (DRD) controller that supports both device and host functions.
| USB3DR speeds supported | SS (5000 Mb/s) | HS (480 Mb/s) | FS (12 Mb/s) | LS (1.5 Mb/s) |
|---|---|---|---|---|
| Host mode | 
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| Device mode |
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USB3DR supports the following PHY interfaces:
| USB3DR peripheral PHY interfaces | STM32MP25x lines 
|
|---|---|
| UTMI interface connected to internal HS PHY for HS/FS/LS speeds |
|
| PIPE interface connected to internal SS PHY for SS speeds |
|
The USB3DR peripheral is fully compliant with:
- Universal Serial Bus Revision 2.0 Specification[1], Revision 2.0, April 27, 2000
- Universal Serial Bus Revision 3.0 Specification[2], Revision 3.0, November 12, 2008
- USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification[3], July 16, 2007
- USB 2.0 Transceiver Macrocell Interface (UTMI) Specification[4], Version 1.05, March 29, 2001
- UTMI+ Specification[5], Revision 1.0, February 25, 2004
- Physical Interface for PCI Express (PIPE) Specification[6], Version 4.00
Refer to the STM32 MPU reference manuals for the complete list of features and to the software frameworks and drivers introduced below to see which features are implemented.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
3.1.1. On STM32MP2 series[edit | edit source]
The USB3DR peripheral is used by ROM code, FSBL, and SSBL in device mode (DFU) to support serial boot for flash programming with STM32CubeProgrammer.
Click on 
to expand or collapse the legend...
- ☐ means that the peripheral can be assigned to the given boot time context.
- ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 non-secure (U-Boot) | |||
| High speed interface | USB3DR | USB3DR | ☐ | ☐ | ☐ | The USB3DR can be used by ROM code, FSBL and SSBL in DFU mode to support serial boot. It can be used also in U-boot with command line tools. |
3.2. Runtime assignment[edit | edit source]
3.2.1. On STM32MP25x lines [edit | edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 non-secure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 non-secure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| High speed interface | USB3DR | USB3DR | ⬚OP-TEE | ☐ | ⬚ | ⬚ | The USB3DR running at USB3 speed and the PCIe are mutually exclusive. Both require to use the ComboPHY. | |
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers managing the USB3DR peripheral for the embedded software components listed in the above tables.
- Linux®: Linux USB framework
- TF-A BL2: USB device framework (drivers/usb/usb_device.c ) and driver (drivers/st/usb_dwc3/usb_dwc3.c )
- U-Boot: UDC framework (drivers/usb/gadget/udc/ ) and driver (drivers/usb/dwc3/dwc3-generic.c )
5. How to assign and configure the peripheral[edit | edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
For Linux kernel configuration, refer to USB3DR device tree configuration.
For U-Boot configuration, refer to Configure USB node in U-Boot.
6. References[edit | edit source]
- ↑ Universal Serial Bus Revision 2.0 Specification
- ↑ Universal Serial Bus Revision 3.0 Specification
- ↑ ECN USB 2.0 Link Power Management Addendum
- ↑ USB 2.0 Transceiver Macrocell Interface (UTMI) Specification
- ↑ UTMI+ Specification
- ↑ PHY Interface for the PCI Express™, SATA, and USB 3.0 Architectures, Intel Corp.
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.