Last edited 3 months ago

LPUART internal peripheral


1. Article purpose[edit | edit source]

The purpose of this article is to:

  • briefly introduce the LPUART peripheral and its main features,
  • indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
  • list the software frameworks and drivers managing the peripheral,
  • explain how to configure the peripheral.

2. Peripheral overview[edit | edit source]

The LPUART peripheral is similar to the UART, with minimum power consumption.

High-speed data communications can be achieved by using the HPDMA or LPDMA for multibuffer configuration.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage[edit | edit source]

3.1. Boot time assignment[edit | edit source]

3.1.1. On STM32MP2 series[edit | edit source]

Click on How to.png to expand or collapse the legend...

Domain Peripheral Boot time allocation Comment How to.png
Instance Cortex-A35
secure
(ROM code)
Cortex-A35
secure
(TF-A BL2)
Cortex-A35
nonsecure
(U-Boot)
Low speed interface LPUART LPUART1

3.2. Runtime assignment[edit | edit source]

3.2.1. On STM32MP21x lines More info.png[edit | edit source]

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A35
secure
(OP-TEE /
TF-A BL31)
Cortex-A35
nonsecure
(Linux)
Cortex-M33
secure
(TF-M)
Cortex-M33
nonsecure
(STM32Cube)
Low speed interface LPUART LPUART1 OP-TEE
TF-A BL31

3.2.2. On STM32MP23x lines More info.png[edit | edit source]

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A35
secure
(OP-TEE /
TF-A BL31)
Cortex-A35
nonsecure
(Linux)
Cortex-M33
secure
(TF-M)
Cortex-M33
nonsecure
(STM32Cube)
Low speed interface LPUART LPUART1 OP-TEE
TF-A BL31

3.2.3. On STM32MP25x lines More info.png[edit | edit source]

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A35
secure
(OP-TEE /
TF-A BL31)
Cortex-A35
nonsecure
(Linux)
Cortex-M33
secure
(TF-M)
Cortex-M33
nonsecure
(STM32Cube)
Cortex-M0+
(STM32Cube)
Low speed interface LPUART LPUART1 OP-TEE
TF-A BL31

4. Software frameworks and drivers[edit | edit source]

The STM32MP2 series devices feature a LPUART instance supporting only Asynchronous mode.

Below are listed the software frameworks and drivers managing the LPUART peripheral for the embedded software components listed in the above tables.

5. How to assign and configure the peripheral[edit | edit source]

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

  • partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
  • HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

See also additional information in the Serial TTY device tree configuration article for Linux®.