Clock device tree configuration

Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to explain how to configure the RCC internal peripheral clocks using the device tree mechanism, relying on the bindings documentation, that is the description of the required and optional device-tree properties.

The peripheral can be assigned to different contexts/software components, depending on the final product needs. Refer to How to assign an internal peripheral to a runtime context article for guidelines on this configuration .

2 DT bindings documentation[edit]

The device tree binding documents are stored either in the given applicable components listed below, or in the Linux kernel repository:

3 DT configuration[edit]

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device-tree file organization.

STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.

3.1 DT configuration (STM32/SoC level)[edit]

The RCC node is located in the device tree file for the software components, supporting the peripheral and listed in the above DT bindings documentation paragraph.

Warning white.png Warning
This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

3.2 DT configuration (board level)[edit]

The objective of this chapter is to explain how to configure a clock tree related to the board.
Using this chapter, the end-user can configure any parameters via the DT to adapt to a new board.

3.2.1 STM32MP15x lines More info.png[edit]

Clock tree configuration it's only done in TF-A BL2. It is only copied in OP-TEE DT for a functional check purpose.

This an example a clock configuration tree:

&rcc {
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MCU_PLL3P
		CLK_PLL12_HSE
		CLK_PLL3_HSE
		CLK_PLL4_HSE
		CLK_RTC_LSE
		CLK_MCO1_DISABLED
		CLK_MCO2_DISABLED
	>;

	st,clkdiv = <
		1 /*MPU*/
		0 /*AXI*/
		0 /*MCU*/
		1 /*APB1*/
		1 /*APB2*/
		1 /*APB3*/
		1 /*APB4*/
		2 /*APB5*/
		23 /*RTC*/
		0 /*MCO1*/
		0 /*MCO2*/
	>;

	st,pkcs = <
		CLK_CKPER_HSE
		CLK_FMC_ACLK
		CLK_QSPI_ACLK
		CLK_ETH_PLL4P
		CLK_SDMMC12_PLL4P
		CLK_DSI_DSIPLL
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_SPI2S1_PLL3Q
		...
	>;

	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
	pll2: st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;
		cfg = <2 65 1 0 0 PQR(1,1,1)>;
		frac = <0x1400>;
	};

	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
	pll3: st,pll@2 {
		compatible = "st,stm32mp1-pll";
		reg = <2>;
		cfg = <1 33 1 16 36 PQR(1,1,1)>;
		frac = <0x1a04>;
	};

	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
	pll4: st,pll@3 {
		compatible = "st,stm32mp1-pll";
		reg = <3>;
		cfg = <3 98 5 7 7 PQR(1,1,1)>;
	};
};

You can find a full example of the board configuration here stm32mp15xx-dkx.dtsi


3.2.2 STM32MP13x lines Warning.png[edit]

Clock tree configuration it's done in TF-A and in OP-TEE.

Usually a minimal configuration is applied in TF-A BL2 and the full configuration in OP-TEE.

This an example a clock configuration tree:

&rcc {
	compatible = "st,stm32mp13-rcc", "syscon", "st,stm32mp13-rcc-mco";
	pinctrl-0 = <&rcc_mco_pins_a>;
	pinctrl-names = "default";

	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MLAHBS_PLL3
		CLK_RTC_LSE
		CLK_MCO1_HSE
		...
	>;

	st,clkdiv = <
		DIV(DIV_MPU, 1)
		DIV(DIV_AXI, 0)
		DIV(DIV_MLAHB, 0)
                ...
	>;

	st,pll_vco {
		pll3_vco_417_8Mhz: pll3-vco-417_8Mhz {
			src = < CLK_PLL3_HSE >;
			divmn = < 1 33 >;
			frac = < 0x1a04 >;
		};

		pll4_vco_600Mhz: pll4-vco-600Mhz {
			src = < CLK_PLL4_HSE >;
			divmn = < 1 49 >;
		};
	};

	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
	pll3:st,pll@2 {
		compatible = "st,stm32mp1-pll";
		reg = <2>;

		st,pll = < &pll3_cfg1 >;

		pll3_cfg1: pll3_cfg1 {
			st,pll_vco = < &pll3_vco_417_8Mhz >;
			st,pll_div_pqr = < 1 16 36 >;
		};
	};

	/* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */
	pll4:st,pll@3 {
		compatible = "st,stm32mp1-pll";
		reg = <3>;
		st,pll = < &pll4_cfg1 >;

		pll4_cfg1: pll4_cfg1 {
			st,pll_vco = < &pll4_vco_600Mhz >;
			st,pll_div_pqr = < 11 59 11 >;
		};
	};
};

You can find a full example of the board configuration here stm32mp135f-dk.dts

4 How to configure the DT using STM32CubeMX[edit]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
STM32CubeMX may not support all the properties described in DT binding files listed in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties, and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

5 References[edit]

Please refer to the following links for additional information: