Last edited one month ago

PCIe internal peripheral

Applicable for STM32MP25x lines

1. Article purpose[edit source]

The purpose of this article is to:

  • briefly introduce the PCIe peripheral and its main features,
  • indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
  • list the software frameworks and drivers managing the peripheral,
  • explain how to configure the peripheral.

2. Peripheral overview[edit source]

The PCIe internal peripheral is based on the Synopsys DesignWare® PCIe controller. It's a PCIe Gen2 controller, hence allowing to communicate by using the PCIe Gen1 or Gen2 protocol. It features a single lane with bidirectional transfer rate of 250MB/s or 500MB/s. The peripheral is a dual role controller, it can operate as a root complex (RC) or as an endpoint (EP). The peripheral is connected to the ComboPHY internal peripheral in PCIe mode, which can provide the 100Mhz reference clock.

The PCIe peripheral main features are the following:

  • Clock 100MHz: External (with SSC), Internal (wo SSC), common clock (bus), core or auxiliary internal clock
  • ASPM: L0s, L1, L1.1
  • AER
  • Max read request size 1K
  • MPS: 256 (Max paquet size) so, 128, 256.
  • Single Virtual channel
  • Single function
  • PTM: Precise Time Measurement

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage[edit source]

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.

3.1. Boot time assignment[edit source]

3.1.1. On STM32MP2 series[edit source]

Click on How to.png to expand or collapse the legend...

  • means that the peripheral can be assigned to the given boot time context.
  • means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
  • means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain Peripheral Boot time allocation Comment How to.png
Instance Cortex-A35
secure
(ROM code)
Cortex-A35
secure
(TF-A BL2)
Cortex-A35
non-secure
(U-Boot)
High speed interface PCIe PCIe The PCIe and the USB3DR running at USB3 speed are mutually exclusive. Both require using the ComboPHY.

3.2. Runtime assignment[edit source]

3.2.1. On STM32MP25x lines More info.png[edit source]

Click on How to.png to expand or collapse the legend...

STM32MP25 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned to the given runtime context.
  • means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A35
secure
(OP-TEE /
TF-A BL31)
Cortex-A35
non-secure
(Linux)
Cortex-M33
secure
(TF-M)
Cortex-M33
non-secure
(STM32Cube)
Cortex-M0+
Warning.png
(STM32Cube)
High speed interface PCIe PCIe OP-TEE The PCIe and the USB3DR running at USB3 speed are mutually exclusive. Both require using the ComboPHY.

4. Software frameworks and drivers[edit source]

Below are listed the software frameworks and drivers managing the PCIe peripheral for the embedded software components listed in the above tables:

5. How to assign and configure the peripheral[edit source]

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral by generating:

  • partial device trees (pin control and clock tree) for the OpenSTLinux software components,
  • HAL initialization code for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

For the Linux kernel, please refer to the PCIe device tree configuration

6. References[edit source]