1. Article purpose[edit | edit source]
The STM32MP23xx/25xx device errata sheet[1] lists the different device limitations and explains the corresponding workarounds (software and/or hardware) if any.
The objective of this article is to explain which of the workarounds, described in this errata sheet, are applicable and implemented in ecosystem release v6.2.0 
.
This article lists
- errata to be workaround by the customers,
- errata workaround implemented in STM32MPU Ecosystem releases,
- and errata not applicable in STM32MPU Ecosystem releases.
Errata, present in STM32MP23xx/25xx device errata sheet[1] and not listed in this article, have no workaround implemented in STM32MPU Ecosystem releases.
2. Legend[edit | edit source]
The section column refers to the number of the erratum chapter in the errata sheet document.
Rev.Y columns , present in the tables below, refer to the availability and status of a given errata workaround for the described erratum in errata sheet document:
- A = workaround available
- P = partial workaround available
- N = no workaround available
- “-” = limitation absent
OpenSTLinux and CubeMP1 columns , present in the tables below, refer to the availability of a workaround for a given STM32MP13 ecosystem release:
- U = workaround to implement by User
- I = workaround Implemented
- NA= Errata Not Applicable in ST software release
Wave your mouse over a status in the table to display the corresponding legend.
3. Workarounds to implement by customer[edit | edit source]
| Function | Section | Limitation | Rev.Y | Rev.X | 
|
|
Comment |
|---|---|---|---|---|---|---|---|
| SYSTEM | 2.3.23 | Standby1/2 exit stuck in Secured_Locked state in A35-TD flavor 
|
A | - | U | Restriction for low-power mode in A35-TD flavor : not supported on secure chips for old revisions.
OpenSTLinux does not provide a workaround (no revision and secure-chip detection). The limitation must be handled in the customer board TF‑A device tree by declaring the supported low-power modes. | |
| 2.3.31 | CPU1 core cannot be reset by CPU0 in 64-bit development boot
mode |
A | - | NA | U | Warning: The errata is incorrect: the issue is not CPU0 vs CPU1 but core0 vs core1 (both are named CPU1 in the reference manual).
Not applicable to OpenSTLinux, as development boot is not used. | |
| FMC | 2.4.1 | NOR flash memory/PSRAM incorrect bus turnaround timing | A | A | U | OpenSTLinux distribution: Delays to apply by customer at device tree level. | |
| OCTOSPI | 2.5.6 | Indirect write mode limited to 256 Mbytes | N | N | U | OpenSTLinux distribution: Memory with a density greater than 256 MB should be avoided. | |
| I3C | 2.15.2 | I3C controller: SCL clock is not stalled during address ACK/NACK phase following a frame start, when enabled through I3C_TIMINGR2 register | A | A | U | OpenSTLinux distribution: STALLA is not set in current I3C implementation. If it is required to be set because of a slow target, workaround have to be implemented by customer. | |
| 2.15.4 | I3C controller: no timestamp on IBI acknowledge when timing control is used in Asynchronous mode 0 | A | A | U | OpenSTLinux distribution: SETXTIME CCC defined but not used yet in Linux OS. This prevents to operate in asynchronous mode. |
4. Workarounds implemented in STM32MP23-25 ecosystem releases[edit | edit source]
| Function | Section | Limitation | Rev.Y | Rev.X |
|
|
Comment |
|---|---|---|---|---|---|---|---|
| SYSTEM | 2.3.5 | Compartment filtering of PWR_CR11 and PWR_CR12 registers is not functional | A | A | I | Workaround implemented in OP-TEE and TF-M: change RIF configuration before register access | |
| 2.3.6 | STGEN is reset when D1 domain is in DStandby low power mode | N | N | I | TF‑BL31: restart STGEN on exit from low-power mode, as STGEN is reset in D1 DStandby mode | ||
| 2.3.19 | STOP and Standby entry failed when DDR is in shared mode | A | A | I | Done for A35-TD, but not as described in the errata: DDR shared mode is deactivated before executing the low-power sequence in TF‑A BL31 | ||
| 2.3.24 | System resources configuration modification by ROM code during D1 DStandby exit | A | - | I | A35-TD flavor : OpenSTLinux keeps the SYSRAM content, and TF‑A BL31 does not allow the behavior described in the errata ( LEGACY_BEN = 1 and Stop2 exit point saved in a BKP register ).
M33-TD flavor | ||
| 2.3.28 | I/O compensation could alter duty-cycle of high-frequency output signal | A | A | I | For OpenSTLinux, IOCOMP is set to static values in TF‑A, OP‑TEE, and TF‑M | ||
| 2.3.29 | Incorrect instance value in boot ROM for eMMC™single device mode in M33-TD flavor
|
A | - | I | Workaround available in TF-A for Rev.Y, issue fixed on Rev.X | ||
| OCTOSPI | 2.5.4 | Deadlock or write-data corruption after spurious write to a misaligned
address in OCTOSPI_AR register |
N | N | I | OpenSTLinux distribution: Misaligned addresses are handled at driver side when DQSE is set. | |
| 2.5.9 | Setting the ABORT bit does not generate an error on the AHB bus for
undefined-length incremental burst transfers |
P | P | I | OpenSTLinux distribution: The software waits for the end of the transfer before setting the ABORT bit. | ||
| I2C | 2.14.1 | Wrong data sampling when data setup time (tSU;DAT) is shorter than one
I2C kernel clock period |
P | P | I | Workaround implemented in device tree with a clock tree that configures the I2C kernel clock source to a frequency higher than 20 MHz. | |
| I3C | 2.15.1 | I3C controller: unexpected read data bytes during a legacy I2C read | A | A | I | OpenSTLinux distribution: STALLT is not set in current I3C implementation. If it is required to be set because of a slow target, workaround is IMPLEMENTED: all I3C/I2C transfers implement a software timeout to inform that neither FCF nor ERRF was raised and FIFOs are flushed. | |
| 2.15.3 | I3C controller: unexpected first frame with a 0x7F address when the I3C
peripheral is enabled |
A | A | I | OpenSTLinux distribution: Workaround implemented in device tree with an 'init' pinctrl state with pull-up on SDA, until I3C controller is enabled. |
5. Workarounds not applicable in STM32MP23-25 ecosystem releases[edit | edit source]
| Function | Section | Limitation | Rev.Y | Rev.X |
|
|
Comment |
|---|---|---|---|---|---|---|---|
| SYSTEM | 2.1.6 | ATS12NSOPR instruction might incorrectly translate when the HCR.TGE bit is set | A | A | NA | Not applicable in OpenSTLinux, as boot is EL3 AArch64 only, while the errata requires EL3 AArch32. | |
| SYSTEM | 2.3.10 | LSEDRV description is swapped | N | N | NA | This errata is for an old reference manual (as indicated).
The new reference manual is updated and OpenSTLinux uses the correct value (TF‑A / OP‑TEE / TF‑M). This is a documentation issue rather than a device limitation. | |
| SYSTEM | 2.3.14 | Instruction fetch access to PWR register leads to unwanted write | A | A | NA | No workaround needed, as PWR is not mapped as code area but as device in both CA35 MMU and CM33 MPU. | |
| SYSTEM | 2.3.17 | ETHx kernel clock is gated if ETHxMACEN register bit is not set | A | A | NA | RCC, Ethernet (Linux® kernel, U‑Boot): ETHxMACEN bit is always enabled by default on all STM32 MPU platforms. | |
| SYSTEM | 2.3.30 | Boot ROM hangs during D1-standby wake-up if e•MMC GPT format is used and FSBL size is less than 512 bytes in M33-TD flavor
|
A | - | NA | FSBL‑A is TF‑A BL2, loaded by the ROM code at the end of SYSRAM, so the stm32image size is greater than 512. The beginning of SYSRAM is reserved for TF‑A BL31, and the TF‑A BL2 stm32 file loaded by the ROM code is filled with 0x0, so its size is larger than the load offset in SYSRAM (0x16000). | |
| FMC | 2.4.2 | Incorrect FMC_CLK clock period when CLKDIV value is changed on-the-fly in continuous clock mode | A | A | NA | OpenSTLinux distribution: CLKDIV cannot be changed on the fly, CLKDIV is configured when the driver is probed. | |
| OCTOSPI | 2.5.1 | Memory-mapped write error response when DQS output is disabled | P | P | NA | OpenSTLinux distribution: memory-mapped write is not used by the software. | |
| 2.5.3 | Memory wrap instruction not enabled when DQS is disabled | N | N | NA | OpenSTLinux distribution: memory wrap instruction is not used by the software. | ||
| 2.5.5 | Deadlock on consecutive out-of-range memory-mapped write operations | P | P | NA | OpenSTLinux distribution: memory-mapped write is not used by the software. | ||
| 2.5.7 | Read-modify-write operation does not clear the MSEL bit | A | A | NA | OpenSTLinux distribution: MSEL bit is never set by the software. | ||
| 2.5.8 | Automatic status-polling mode cannot be used with HyperFlash™ memories | N | N | NA | OpenSTLinux distribution: automatic status-polling mode is not used by the software with HyperFlash memories. | ||
| 2.5.10 | Read data corruption when a wrap transaction is followed by a linear read to the same MSB address | N | N | NA | OpenSTLinux distribution: memory wrap instruction is not used by the software. | ||
| 2.5.11 | Transactions are limited to 8 Mbytes in OctaRAM™ memories | N | N | NA | OpenSTLinux distribution: OctaRAM memories are not supported by the software (the driver is not available). | ||
| 2.5.12 | Variable latency is not supported when a refresh collision occurs during a write access to some OctaRAM™ memories | P | P | NA | OpenSTLinux distribution: OctaRAM memories are not supported by the software (the driver is not available). | ||
| OCTOSPIM | 2.6.1 | Certain quad memories may be reset during arbitration while in single-SPI mode | A | A | NA | OpenSTLinux distribution: not an issue from software side, as the frameworks (SPI NOR/SPI NAND) start by setting the memory in quad mode. | |
| SDMMC | 2.7.1 | Command response and receive data end bits not checked | N | N | NA | OpenSTLinux distribution: not an issue from software side, as it is not visible by the software. | |
| I2C | 2.14.2 | Spurious bus error detection in controller mode | A | A | NA | In order to get real bus error notifications, this workaround is not implemented in the OpenSTLinux distribution. | |
| USART | 2.16.1 | Wrong data received by SPI slave receiver in autonomous mode with CPOL = 1 | A | A | NA | OpenSTLinux distribution: SPI slave mode is not implemented. | |
| 2.16.2 | Received data may be corrupted upon clearing the ABREN bit | A | A | NA | OpenSTLinux distribution: condition never reached in Linux OS thanks to the specific implementation (ABREN bit never cleared in USART_CR2 register). | ||
| 2.16.3 | Noise error flag set while ONEBIT is set | N | N | NA | OpenSTLinux distribution: not applicable as the Linux framework does not handle the noise error indication. | ||
| LPUART | 2.17.1 | Possible LPUART transmitter issue when using low BRR[15:0] value | P | P | NA | OpenSTLinux distribution: LPUART kernel clock and baudrate ratio prevent these cases. To reach these cases, LPUART kernel clock should be 3 or 4 times greater than the baudrate, but LPUART kernel clock sources are ≥ 16 MHz. | |
| SPI | 2.18.1 | RDY output failure at high serial clock frequency | N | N | NA | The APB clock and SPI kernel clock ratio defined in the OpenSTLinux distribution prevent these cases from occurring. The APB clock is set to 200 MHz, and the SPI kernel clock is set to either 133 MHz or 200 MHz. |
6. References[edit | edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 