1. Article purpose[edit source]
The purpose of this article is to explain how to configure the WLAN when the peripheral (or peripheral associated to the framework) is assigned to Linux® OS.
The configuration is performed using the device tree mechanism that provides a hardware description of the WLAN peripheral connected on SDIO bus.
The purpose of this article is to explain Cypress WLAN/BT companion chip device tree node
- for STM32MP13x lines and STM32MP15x lines [1]
- for STM32MP25x lines [2]
2. DT bindings documentation[edit source]
The WLAN[3] tree bindings are composed by :
- SDIO link configuration[4]
- WLAN device configuration[5]
3. DT configuration[edit source]
This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.
3.1. DT configuration (STM32 level)[edit source]
The companion chip uses the SDIO link so the DT is based on the SDMMC peripheral node which is located
- for STM32MP13x lines in stm32mp131.dtsi [6]
- for STM32MP15x lines in stm32mp151.dtsi [7]
- for STM32MP25x lines in stm32mp251.dtsi [8]
This is a set of properties that may not vary for given STM32 device, such as: registers address, clock, reset. The SDMMC DT configuration is explained at SDMMC device tree configuration
3.2. DT configuration (board level)[edit source]
Part of the device tree is used to describe the WLAN hardware used on a given board. The DT node ("sdmmc2") must be filled in:
- mmc-pwrseq: phandle to the MMC power sequence node
&sdmmc2 { ... arm,primecell-periphid = <0x10153180>; /* Mandatory version for SDIO */ ... non-removable; st,neg-edge; bus-width = <4>; vmmc-supply = <&v3v3>; mmc-pwrseq = <&wifi_pwrseq>; /* phandle to the MMC power sequence node */ ... brcmf: bcrmf@1 { /* node of WLAN companion chip */ reg = <1>; compatible = "brcm,bcm4329-fmac"; } }
The arm,primecell-periphid property has to be forced to <0x10153180> for SDIO. Setting this version disables the support for Linked List in the SDMMC Internal DMA. Linked List mandates all the blocks in the list (except the last one) are the same size, which cannot be satisfied with SDIO.
4. References[edit source]