1. Article purpose[edit | edit source]
The purpose of this article is to explain how to configure the QUADSPI using the device tree mechanism, relying on the bindings documentation, that is the description of the required and optional device-tree properties.
The peripheral can be assigned to different contexts/software components, depending on the final product needs. Refer to How to assign an internal peripheral to an execution context article for guidelines on this configuration.
2. DT bindings documentation[edit | edit source]
The device tree binding documents are stored either in the given applicable components listed below, or in the Linux kernel repository:
- TF-A BL2, U-Boot, OP-TEE, Linux® OS:
- Generic SPI-NOR / SPI-NAND Flash memory device tree bindings: Documentation/devicetree/bindings/spi/spi-controller.yaml .
- QUADSPI device tree bindings: Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml .
3. DT configuration[edit | edit source]
This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device-tree file organization.
STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.
3.1. DT configuration (STM32 level)[edit | edit source]
The QUADSPI node is located in the device tree file for the software components, supporting the peripheral and listed in the above DT bindings documentation paragraph.
3.2. DT configuration (board level)[edit | edit source]
The objective of this chapter is to explain how to enable and configure the QUADSPI DT nodes for a board.
Peripheral configuration should be done in specific board device tree files (board dts file and pinctrl dtsi file).
&qspi { Comments
pinctrl-names = "default", "sleep"; --> For pinctrl configuration, please refer to Pinctrl device tree configuration
pinctrl-0 = <&qspi_clk_test_pins_a
&qspi_bk1_test_pins_b
&qspi_cs1_test_pins_b
&qspi_bk2_test_pins_b
&qspi_cs2_test_pins_b>;
pinctrl-1 = <&qspi_clk_test_sleep_pins_a
&qspi_bk1_test_sleep_pins_b
&qspi_cs1_test_sleep_pins_b
&qspi_bk2_test_sleep_pins_b
&qspi_cs2_test_sleep_pins_b>;
reg = <0x58003000 0x1000>,
<0x70000000 0x4000000>; --> Overwrite the memory map to the Flash device size, avoid the waste of virtual memory that will not be used
#address-cells = <1>;
#size-cells = <0>;
status = "okay"; --> Enable the node
flash0: mx66l51235l@0 {
compatible = "jedec,spi-nor";
reg = <0>; --> Chip select number
spi-rx-bus-width = <4>; --> The bus width (number of data wires used)
spi-max-frequency = <108000000>; --> Maximum SPI clocking speed of device in Hz
#address-cells = <1>;
#size-cells = <1>;
};
};
3.3. DT configuration example[edit | edit source]
The below example shows how to configure the QUADSPI peripheral when 1 SPI-NAND Flash and 1 SPI-NOR Flash memories are connected.
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_test_pins_a
&qspi_bk1_test_pins_b
&qspi_cs1_test_pins_b
&qspi_bk2_test_pins_b
&qspi_cs2_test_pins_b>;
pinctrl-1 = <&qspi_clk_test_sleep_pins_a
&qspi_bk1_test_sleep_pins_b
&qspi_cs1_test_sleep_pins_b
&qspi_bk2_test_sleep_pins_b
&qspi_cs2_test_sleep_pins_b>;
reg = <0x58003000 0x1000>,
<0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: mx66l51235l@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
flash1: mt29f2g01abagd@1 {
compatible = "spi-nand";
reg = <1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <133000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
The below example, possible with ecosystem release ≥ v4.1.0 , shows how to configure the QUADSPI peripheral to use it as a communication channel using up to 8 qspi lines. It can be used to communicate with a FPGA. To enable the usage of the 8 qspi lines, the following properties are mandatory:
- the chip select pins need to be removed from pinctrl-0 and pinctrl-1 properties.
- cs-gpios properties must be populated in the controller node.
- spi-rx-bus-width and spi-tx-bus-width properties must be set to 8 in the device node.
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_test_pins_a
&qspi_bk1_test_pins_b
&qspi_bk2_test_pins_b>;
pinctrl-1 = <&qspi_clk_test_sleep_pins_a
&qspi_bk1_test_sleep_pins_b
&qspi_bk2_test_sleep_pins_b>;
reg = <0x58003000 0x1000>,
<0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
cs-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>;
fpga@0 {
compatible = "fpga";
reg = <0>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <8>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
4. How to configure the DT using STM32CubeMX[edit | edit source]
The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
STM32CubeMX may not support all the properties described in DT binding files listed in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties, and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.
5. References[edit | edit source]
Refer to the following links for additional information:
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