Last edited one year ago

Arm Cortex-A7

Applicable for STM32MP13x lines, STM32MP15x lines

1. Article purpose[edit source]

The purpose of this article is to:

  • briefly introduce the Arm® Cortex®-A7 core and its main features,
  • indicate the level of security supported by this processor.

2. Peripheral overview[edit source]

The Arm Cortex-A7 can be instantiated several times into a single cluster:

  • The STM32MP13 main processor is a Cortex-A7 cluster embedding a single core.
  • The STM32MP15 main processor is a Cortex-A7 cluster embedding one or two core(s), depending on the selected line.

The Cortex-A7 is a 32-bit processor that belongs to ARMv7-VE architecture family. ARMv7-VE corresponds to the ARMv7-A architecture, with virtual extensions. Among a wide range of features, it includes a memory management unit (MMU), a separate L1 cache and a unified L2 cache in order to efficiently support rich operating systems such as Linux, with a high level of performance.

The Cortex-A7 supports a non-secure and a secure modes that define two hardware execution contexts, named Cortex-A7 non-secure and Cortex-A7 secure.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage[edit source]

3.1. Boot time assignment[edit source]

As soon as the STM32MP1 is powered up, the Cortex-A7 starts to execute the ROM code, which is the first stage of the boot chain. It then executes the FSBL TF-A in secure mode before jumping to the SSBL U-Boot in non-secure mode.

3.2. Runtime assignment[edit source]

The Cortex-A7 is the main processor supporting Cortex-A7 secure and Cortex-A7 non-secure contexts. It therefore cannot be assigned but, it manages all the peripherals assigned to those contexts.

4. Software frameworks and drivers[edit source]

All the software components executed by the Cortex-A7, at boot time and at runtime, constitute the OpenSTLinux distribution.

Below are listed the software frameworks and drivers managing the XXX peripheral for the embedded software components listed in the above tables.

5. How to assign and configure the peripheral[edit source]

The Cortex-A7 configuration is done by the various components running on it, according to build-time parameters, and also information from the device tree.

6. How to go further[edit source]

Refer to Arm website[1] for more detailed information on this core.

7. References[edit source]