DCMI device tree configuration

Applicable for

STM32MP15x lines, Unknown MPU, Unknown MPU, STM32MP25x lines

---

1. Article purpose

This article explains how to configure the DCMI internal peripheral when assigned to the Linux^® OS. In that case, it is controlled by the V4L2 camera framework.

The configuration is performed using the device tree mechanism that provides a hardware description of the DCMI peripheral, used by the STM32 DCMI Linux driver or by the V4L2 camera framework.

If the peripheral is assigned to another execution context, refer to How to assign an internal peripheral to an execution context article for guidelines on peripheral assignment and configuration.

2. DT bindings documentation

The DCMI internal peripheral is documented through the STM32 DCMI device tree bindings file Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml .

3. DT configuration

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the device tree article for an explanation of the device tree file split.

STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.

3.1. DT configuration (STM32/SoC level)

3.1.1. For STM32MP15x lines 

The DCMI device tree node is declared in arch/arm/boot/dts/st/stm32mp151.dtsi . The declaration (shown below) provides the hardware registers base address, interrupts, reset line, clocks and dma channel used.

...
		etzpc: bus@5c007000 {
...
			dcmi: dcmi@4c006000 {
				compatible = "st,stm32-dcmi";
				reg = <0x4c006000 0x400>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				resets = <&rcc CAMITF_R>;
				clocks = <&rcc DCMI>;
				clock-names = "mclk";
				dmas = <&dmamux1 75 0x400 0x01>;
				dma-names = "tx";
				access-controllers = <&etzpc 70>;
				status = "disabled";
			};
...

Warning

This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

When using a different sensor camera device, only the sensor-related configuration part must be adapted in the associated board device tree file (see DT configuration (board level) chapter).

Information

DCMI capture performance can be increased by relying on a 2nd DMA channel and SRAM located intermediate buffer in order to achieve DMA / MDMA chaining. DCMI driver is configured to achieve this by giving a 2nd DMA channel entry and a sram pool phandle into the dcmi node. Such configuration is done in the board DT, the following section gives such example. Refer to stm32-dcmi bindings for more details.

3.1.2. For STM32MP2 series

The DCMIPP device tree node is declared in:

Click here to show the example

• arch/arm64/boot/dts/st/stm32mp211.dtsi on STM32MP21 unknown microprocessor device

...
	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <2>;
		interrupt-parent = <&intc>;
		ranges = <0x0 0x0 0x0 0x0 0x80000000>;
		dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>;
...
			dcmi: dcmi@404a0000 {
				compatible = "st,stm32-dcmi";
				reg = <0x404a0000 0x0 0x400>;
				interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
				resets = <&rcc DCMIPSSI_R>;
				clocks = <&rcc CK_BUS_DCMIPSSI>;
				clock-names = "mclk";
				dmas = <&hpdma 105 0x60 0x3012>;
				dma-names = "tx";
				access-controllers = <&rifsc 88>;
				status = "disabled";
			};
...

Click here to show the example

• arch/arm64/boot/dts/st/stm32mp231.dtsi on STM32MP23 unknown microprocessor device

...
		rifsc: bus@42080000 {
...
			dcmi: dcmi@404a0000 {
				compatible = "st,stm32-dcmi";
				reg = <0x404a0000 0x400>;
				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
				resets = <&rcc CCI_R>;
				clocks = <&rcc CK_BUS_CCI>;
				clock-names = "mclk";
				dmas = <&hpdma 137 0x60 0x00003012>;
				dma-names = "tx";
				access-controllers = <&rifsc 88>;
				power-domains = <&CLUSTER_PD>;
				status = "disabled";
			};
...

Click here to show the example

• arch/arm64/boot/dts/st/stm32mp251.dtsi on STM32MP25x lines 

...
		rifsc: bus@42080000 {
...
			dcmi: dcmi@404a0000 {
				compatible = "st,stm32-dcmi";
				reg = <0x404a0000 0x400>;
				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
				resets = <&rcc CCI_R>;
				clocks = <&rcc CK_BUS_CCI>;
				clock-names = "mclk";
				dmas = <&hpdma 137 0x60 0x00003012>;
				dma-names = "tx";
				access-controllers = <&rifsc 88>;
				power-domains = <&CLUSTER_PD>;
				status = "disabled";
			};
...

Warning

This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

When using a different sensor camera device, only the sensor-related configuration part must be adapted in the associated board device tree file (see DT configuration (board level) chapter).

3.2. DT configuration (board level)

3.2.1. For STM32MP15x lines 

&dcmi {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&dcmi_pins_a>;
	pinctrl-1 = <&dcmi_sleep_pins_a>;

	/*
	 * Enable DMA-MDMA chaining by adding a SRAM pool and
	 * a MDMA channel
	 */
	sram = <&dcmi_pool>;

	dmas = <&dmamux1 75 0x400 0x01>, <&mdma1 0 0x3 0x1200000a 0 0>;
	dma-names = "tx", "mdma_tx";

	port {
		dcmi_0: endpoint {
			remote-endpoint = <&ov5640_0>;
			bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
			bus-width = <8>;
			hsync-active = <0>;
			vsync-active = <0>;
			pclk-sample = <1>;
			pclk-max-frequency = <77000000>;
		};
	};
};
...
&i2c2 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c2_pins_a>;
	pinctrl-1 = <&i2c2_sleep_pins_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "okay";
...
	ov5640: camera@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		clocks = <&clk_ext_camera>;
		clock-names = "xclk";
		AVDD-supply = <&v2v8>;
		DOVDD-supply = <&v2v8>;
		DVDD-supply = <&v2v8>;
		powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
		reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
		rotation = <180>;
		status = "okay";

		port {
			ov5640_0: endpoint {
				remote-endpoint = <&dcmi_0>;
				bus-width = <8>;
				data-shift = <2>; /* lines 9:2 are used */
				hsync-active = <0>;
				vsync-active = <0>;
				pclk-sample = <1>;
				pclk-max-frequency = <77000000>;
			};
		};
	};
...

&sram4 {
	dcmi_pool: dcmi-pool@0 {
		reg = <0x0 0x8000>;
		pool;
	};
};
...

This section, part of the STM32MP157x-EV1 Evaluation board device tree file arch/arm/boot/dts/st/stm32mp157f-ev1.dts , shows how is configured the DCMI hardware block to interconnect with the sensor camera device. In this example, DMA-MDMA chaining is enabled by allocating a buffer area within the SRAM and updating the dmas property of the dcmi node to indicate both DMA and MDMA channels. The configurable settings are the following:

• Camera sensor endpoint: in this case, the Omnivision OV5640 model connected to the MB1379 camera daughterboard.
• Bus width: 8, 10, 12 or 14 bits
• Horizontal synchronization line level: active low (0) or active high (1)
• Vertical synchronization line level: active low (0) or active high (1)
• Pixel clock polarity line level: active low (0) or active high (1)
• Pixel clock maximum frequency in Hertz

This section also defines what is the DCMI pins multiplexing used for this board (<&dcmi_pins_a>, <&dcmi_sleep_pins_a>), exact pins details being defined in the STM32MP15 evaluation board pinctrl device tree file arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi :

			dcmi_pins_a: dcmi-0 {
				pins {
					pinmux = <STM32_PINMUX('H', 8,  AF13)>,/* DCMI_HSYNC */
						 <STM32_PINMUX('B', 7,  AF13)>,/* DCMI_VSYNC */
						 <STM32_PINMUX('A', 6,  AF13)>,/* DCMI_PIXCLK */
						 <STM32_PINMUX('H', 9,  AF13)>,/* DCMI_D0 */
						 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
						 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
						 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
						 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
						 <STM32_PINMUX('I', 4,  AF13)>,/* DCMI_D5 */
						 <STM32_PINMUX('B', 8,  AF13)>,/* DCMI_D6 */
						 <STM32_PINMUX('E', 6,  AF13)>,/* DCMI_D7 */
						 <STM32_PINMUX('I', 1,  AF13)>,/* DCMI_D8 */
						 <STM32_PINMUX('H', 7,  AF13)>,/* DCMI_D9 */
						 <STM32_PINMUX('I', 3,  AF13)>,/* DCMI_D10 */
						 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
					bias-disable;
				};
			};

			dcmi_sleep_pins_a: dcmi-sleep-0 {
				pins {
					pinmux = <STM32_PINMUX('H', 8,  ANALOG)>,/* DCMI_HSYNC */
						 <STM32_PINMUX('B', 7,  ANALOG)>,/* DCMI_VSYNC */
						 <STM32_PINMUX('A', 6,  ANALOG)>,/* DCMI_PIXCLK */
						 <STM32_PINMUX('H', 9,  ANALOG)>,/* DCMI_D0 */
						 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
						 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
						 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
						 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
						 <STM32_PINMUX('I', 4,  ANALOG)>,/* DCMI_D5 */
						 <STM32_PINMUX('B', 8,  ANALOG)>,/* DCMI_D6 */
						 <STM32_PINMUX('E', 6,  ANALOG)>,/* DCMI_D7 */
						 <STM32_PINMUX('I', 1,  ANALOG)>,/* DCMI_D8 */
						 <STM32_PINMUX('H', 7,  ANALOG)>,/* DCMI_D9 */
						 <STM32_PINMUX('I', 3,  ANALOG)>,/* DCMI_D10 */
						 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
				};
			};

An alternate pin multiplexing could be defined (for example to fit a new board design) by modifying the STM32MP15 evaluation board pinctrl device tree file following the possible pins assignment defined in the MPU reference manual.

STM32CubeMX pins configurator is of great help to find valid alternatives thanks to its visual GUI.

Refer to STM32 DCMI bindings for more details.

3.2.2. For STM32MP2 series

Information

The camera sensor parallel interface is not available on official STM32MP2 boards because the MIPI CSI interface is preferred. However, please find a full example in the chapter DT configuration examples.

The DCMI camera sensor parallel interface pins multiplexing are declared in:

Click here to show the example

• arch/arm64/boot/dts/st/stm32mp23-pinctrl.dtsi on STM32MP23 unknown microprocessor device

...
&pinctrl {
...
	dcmi_test_pins_a: dcmi-test-0 {
		pin_pixclk {
			pinmux = <STM32_PINMUX('G', 5,  AF14)>;/* DCMI_PIXCLK */
			bias-disable;
		};
		pins_sync_data {
			pinmux = <STM32_PINMUX('G', 6,  AF14)>,/* DCMI_HSYNC */
				 <STM32_PINMUX('G', 7,  AF14)>,/* DCMI_VSYNC */
				 <STM32_PINMUX('F', 12, AF14)>,/* DCMI_D0 */
				 <STM32_PINMUX('I', 5,  AF14)>,/* DCMI_D1 */
				 <STM32_PINMUX('G', 8,  AF14)>,/* DCMI_D2 */
				 <STM32_PINMUX('G', 9,  AF14)>,/* DCMI_D3 */
				 <STM32_PINMUX('G', 10, AF14)>,/* DCMI_D4 */
				 <STM32_PINMUX('G', 11, AF14)>,/* DCMI_D5 */
				 <STM32_PINMUX('G', 12, AF14)>,/* DCMI_D6 */
				 <STM32_PINMUX('G', 13, AF14)>;/* DCMI_D7 */
			bias-disable;
			st,io-retime = <1>;
			st,io-clk-type = <1>;
		};
	};

	dcmi_sleep_test_pins_a: dcmi-sleep-test-0 {
		pins {
			pinmux = <STM32_PINMUX('G', 6,  ANALOG)>,/* DCMI_HSYNC */
				 <STM32_PINMUX('G', 7,  ANALOG)>,/* DCMI_VSYNC */
				 <STM32_PINMUX('G', 5,  ANALOG)>,/* DCMI_PIXCLK */
				 <STM32_PINMUX('F', 12, ANALOG)>,/* DCMI_D0 */
				 <STM32_PINMUX('I', 5,  ANALOG)>,/* DCMI_D1 */
				 <STM32_PINMUX('G', 8,  ANALOG)>,/* DCMI_D2 */
				 <STM32_PINMUX('G', 9,  ANALOG)>,/* DCMI_D3 */
				 <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D4 */
				 <STM32_PINMUX('G', 11, ANALOG)>,/* DCMI_D5 */
				 <STM32_PINMUX('G', 12, ANALOG)>,/* DCMI_D6 */
				 <STM32_PINMUX('G', 13, ANALOG)>;/* DCMI_D7 */
		};
	};

	dcmi_test_pins_b: dcmi-test-1 {
		pin_pixclk {
			pinmux = <STM32_PINMUX('G', 3,  AF14)>;/* DCMI_PIXCLK */
			bias-disable;
			slew-rate = <3>;
		};
		pins_sync_data {
			pinmux = <STM32_PINMUX('F', 3,  AF14)>,/* DCMI_HSYNC */
				 <STM32_PINMUX('G', 4,  AF14)>,/* DCMI_VSYNC */
				 <STM32_PINMUX('D', 15, AF13)>,/* DCMI_D0 */
				 <STM32_PINMUX('D', 14,  AF13)>,/* DCMI_D1 */
				 <STM32_PINMUX('K', 7,  AF13)>,/* DCMI_D2 */
				 <STM32_PINMUX('K', 3,  AF13)>,/* DCMI_D3 */
				 <STM32_PINMUX('I', 14, AF13)>,/* DCMI_D4 */
				 <STM32_PINMUX('K', 6, AF13)>,/* DCMI_D5 */
				 <STM32_PINMUX('K', 2, AF13)>,/* DCMI_D6 */
				 <STM32_PINMUX('J', 6, AF13)>;/* DCMI_D7 */
			bias-disable;
			st,io-retime = <1>;
			slew-rate = <3>;
		};
	};

	dcmi_sleep_test_pins_b: dcmi-sleep-test-1 {
		pins {
			pinmux = <STM32_PINMUX('F', 3,  ANALOG)>,/* DCMI_HSYNC */
				 <STM32_PINMUX('G', 4,  ANALOG)>,/* DCMI_VSYNC */
				 <STM32_PINMUX('G', 3,  ANALOG)>,/* DCMI_PIXCLK */
				 <STM32_PINMUX('D', 15, ANALOG)>,/* DCMI_D0 */
				 <STM32_PINMUX('D', 14,  ANALOG)>,/* DCMI_D1 */
				 <STM32_PINMUX('K', 7,  ANALOG)>,/* DCMI_D2 */
				 <STM32_PINMUX('K', 3,  ANALOG)>,/* DCMI_D3 */
				 <STM32_PINMUX('I', 14, ANALOG)>,/* DCMI_D4 */
				 <STM32_PINMUX('K', 6, ANALOG)>,/* DCMI_D5 */
				 <STM32_PINMUX('K', 2, ANALOG)>,/* DCMI_D6 */
				 <STM32_PINMUX('J', 6, ANALOG)>;/* DCMI_D7 */
		};
	};
...

Click here to show the example

• arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi on STM32MP25x lines 

...
&pinctrl {
...
	dcmi_test_pins_a: dcmi-test-0 {
		pin_pixclk {
			pinmux = <STM32_PINMUX('G', 5,  AF14)>;/* DCMI_PIXCLK */
			bias-disable;
		};
		pins_sync_data {
			pinmux = <STM32_PINMUX('G', 6,  AF14)>,/* DCMI_HSYNC */
				 <STM32_PINMUX('G', 7,  AF14)>,/* DCMI_VSYNC */
				 <STM32_PINMUX('F', 12, AF14)>,/* DCMI_D0 */
				 <STM32_PINMUX('I', 5,  AF14)>,/* DCMI_D1 */
				 <STM32_PINMUX('G', 8,  AF14)>,/* DCMI_D2 */
				 <STM32_PINMUX('G', 9,  AF14)>,/* DCMI_D3 */
				 <STM32_PINMUX('G', 10, AF14)>,/* DCMI_D4 */
				 <STM32_PINMUX('G', 11, AF14)>,/* DCMI_D5 */
				 <STM32_PINMUX('G', 12, AF14)>,/* DCMI_D6 */
				 <STM32_PINMUX('G', 13, AF14)>;/* DCMI_D7 */
			bias-disable;
			st,io-retime = <1>;
			st,io-clk-type = <1>;
		};
	};

	dcmi_sleep_test_pins_a: dcmi-sleep-test-0 {
		pins {
			pinmux = <STM32_PINMUX('G', 6,  ANALOG)>,/* DCMI_HSYNC */
				 <STM32_PINMUX('G', 7,  ANALOG)>,/* DCMI_VSYNC */
				 <STM32_PINMUX('G', 5,  ANALOG)>,/* DCMI_PIXCLK */
				 <STM32_PINMUX('F', 12, ANALOG)>,/* DCMI_D0 */
				 <STM32_PINMUX('I', 5,  ANALOG)>,/* DCMI_D1 */
				 <STM32_PINMUX('G', 8,  ANALOG)>,/* DCMI_D2 */
				 <STM32_PINMUX('G', 9,  ANALOG)>,/* DCMI_D3 */
				 <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D4 */
				 <STM32_PINMUX('G', 11, ANALOG)>,/* DCMI_D5 */
				 <STM32_PINMUX('G', 12, ANALOG)>,/* DCMI_D6 */
				 <STM32_PINMUX('G', 13, ANALOG)>;/* DCMI_D7 */
		};
	};

	dcmi_test_pins_b: dcmi-test-1 {
		pin_pixclk {
			pinmux = <STM32_PINMUX('G', 3,  AF14)>;/* DCMI_PIXCLK */
			bias-disable;
			slew-rate = <3>;
		};
		pins_sync_data {
			pinmux = <STM32_PINMUX('F', 3,  AF14)>,/* DCMI_HSYNC */
				 <STM32_PINMUX('G', 4,  AF14)>,/* DCMI_VSYNC */
				 <STM32_PINMUX('D', 15, AF13)>,/* DCMI_D0 */
				 <STM32_PINMUX('D', 14,  AF13)>,/* DCMI_D1 */
				 <STM32_PINMUX('K', 7,  AF13)>,/* DCMI_D2 */
				 <STM32_PINMUX('K', 3,  AF13)>,/* DCMI_D3 */
				 <STM32_PINMUX('I', 14, AF13)>,/* DCMI_D4 */
				 <STM32_PINMUX('K', 6, AF13)>,/* DCMI_D5 */
				 <STM32_PINMUX('K', 2, AF13)>,/* DCMI_D6 */
				 <STM32_PINMUX('J', 6, AF13)>;/* DCMI_D7 */
			bias-disable;
			st,io-retime = <1>;
			slew-rate = <3>;
		};
	};

	dcmi_sleep_test_pins_b: dcmi-sleep-test-1 {
		pins {
			pinmux = <STM32_PINMUX('F', 3,  ANALOG)>,/* DCMI_HSYNC */
				 <STM32_PINMUX('G', 4,  ANALOG)>,/* DCMI_VSYNC */
				 <STM32_PINMUX('G', 3,  ANALOG)>,/* DCMI_PIXCLK */
				 <STM32_PINMUX('D', 15, ANALOG)>,/* DCMI_D0 */
				 <STM32_PINMUX('D', 14,  ANALOG)>,/* DCMI_D1 */
				 <STM32_PINMUX('K', 7,  ANALOG)>,/* DCMI_D2 */
				 <STM32_PINMUX('K', 3,  ANALOG)>,/* DCMI_D3 */
				 <STM32_PINMUX('I', 14, ANALOG)>,/* DCMI_D4 */
				 <STM32_PINMUX('K', 6, ANALOG)>,/* DCMI_D5 */
				 <STM32_PINMUX('K', 2, ANALOG)>,/* DCMI_D6 */
				 <STM32_PINMUX('J', 6, ANALOG)>;/* DCMI_D7 */
		};
	};
...

An alternate pin multiplexing could be defined (for example to fit a new board design) by using the Linux kernel STM32MP25 pinctrl device tree file arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi following the possible pins assignment defined in the MPU reference manual.

STM32CubeMX pins configurator is of great help to find valid alternatives thanks to its visual GUI.

Refer to STM32 DCMI bindings for more details.

3.3. DT configuration examples

Documentation on various V4L2 camera sensors can be found inside I2C media bindings folder. Refer to the dedicated sensor binding documentation to adapt your board device tree file to this dedicated sensor.

3.3.1. For STM32MP15x lines 

Please refer to the example presented in the previous chapter DT configuration (board level).

3.3.2. For STM32MP2 series

The below example described a board device tree using the DCMI with the MB1379 camera daughterboard (Omnivision ov5640 camera sensor):

...
&dcmi {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&dcmi_test_pins_b>;
	pinctrl-1 = <&dcmi_sleep_test_pins_b>;

	port {
		dcmi_0: endpoint {
			remote-endpoint = <&ov5640_0>;
			bus-type = <5>;
			bus-width = <8>;
			hsync-active = <0>;
			vsync-active = <0>;
			pclk-sample = <1>;
		};
	};
};
...
&i2c2 {
...
	ov5640: camera@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		clocks = <&clk_ext_camera>;
		clock-names = "xclk";
		rotation = <180>;
		/*
		 * powerdown / reset differ between the MB1723 (CSI-2) and the MB1379 (Parallel)
		 * Following properties dedicated to CSI-2 should replace the existing ones
		 * if the OV5640 is used in CSI-2 mode
		 * powerdown-gpios = <&gpiok 1 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
		 * reset-gpios = <&gpiok 0 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
		 */
		powerdown-gpios = <&gpiok 0 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
		reset-gpios = <&gpiok 1 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
		status = "okay";

		port {
			ov5640_0: endpoint {
				/*
				 * Following properties are CSI-2 specifics and should only be
				 * defined when the OV5640 is used in CSI-2 mode.  They should
				 * replace the other properties dedicated to parallel interface
				 */
				/* data-lanes = <0 1>; */
				/* link-frequencies = /bits/ 64 <456000000>; */
				/* remote-endpoint = <&csi_sink>; */
				remote-endpoint = <&dcmi_0>;
				bus-type = <5>;
				bus-width = <8>;
				data-shift = <2>; /* lines 9:2 are used */
				hsync-active = <0>;
				vsync-active = <0>;
				pclk-sample = <1>;
				pclk-max-frequency = <77000000>;
			};
		};
	};
...
};
...

4. How to configure the DT using STM32CubeMX

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

5. References

Please refer to the following links for additional information:

Microprocessor unit

Linux^® is a registered trademark of Linus Torvalds.

Operating system

Digital camera memory interface

Video 4 Linux^® version 2

Device tree

Generic interrupt controller

Serial peripheral interface

Direct memory access

Digital camera memory interface pixel processor

General-purpose input/output (A realization of open ended transmission between devices on an embedded level. These pins available on a processor can be programmed to be used to either accept input or provide output to external devices depending on user desires and applications requirements.)

Graphical user interface

Mobile industry processor interface, open membership organization that includes leading companies in the mobile industry that share the objective of defining and promoting open specifications for interfaces inside mobile terminals, see MIPI^® Alliance standard web site https://www.mipi.org

Multi speed internal oscillator (STM32 clock source)

Inter-integrated circuit (Bi-directional 2-wire bus standard for efficient inter-IC control.)

MIPI camera serial interface 2 (MIPI^® Alliance standard)