Difference between revisions of "Arm Cortex-M4"

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Applicable for STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to:

  • briefly introduce the Arm® Cortex®-M4 core and its main features
  • indicate the level of security supported by this processor

2 Peripheral overview[edit]

The Arm Cortex-M4 is seen as a coprocessor on STM32MP15, where the Arm Cortex-A7 is the main processor that controls it. The Cortex-M4 is present across all the STM32MP15x lines.

2.1 Features[edit]

The Cortex-M4 is a 32-bit processor that belongs to the Armv7E-M architecture family. Armv7E-M corresponds to the ARMv7-M architecture, with DSP extension. Among a wide range of features, it includes a memory protection unit (MPU) and a single-precision floating point unit (FPU).

Refer to the STM32MP15 reference manuals for the complete list of features.

2.2 Security support[edit]

The Cortex-M4 does not support secure mode: it only supports a non-secure mode that defines the Cortex-M4 non-secure hardware execution context.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The STM32CubeMP1 package execution startup on the Cortex-M4 coprocessor is controlled by the Cortex-A7, that is running the OpenSTLinux distribution.

The coprocessor startup can be done at two different stages of the boot chain:

Thanks to a specific OP-TEE trusted application (TA) running on the Arm® TrustZone and to the ETZPC peripheral, it is possible to authenticate the Cortex®-M4 firmware and install it on isolated MCU RAM to ensure its integrity during the execution. For details, please refer to How_to_protect_the_coprocessor_firmware article.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The Cortex-M4 runs the STM32CubeMP1 package.

The Cortex-M4 operates as a coprocessor, either autonomously as any external microcontroller (such as an STM32F4) could, or communicating with the main processor (Cortex-A7) via the RPMsg communication pipe.

3.2.2 Software frameworks[edit]

Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Ecosystem Cortex-M4 STM32CubeMP1 package

3.2.3 Peripheral configuration[edit]

The Cortex-M4 configuration is done in two steps:

  1. As the main processor of the system, the Cortex-A7 (running OpenSTLinux distribution) first takes care of the initialization of all system resources: supplies, clock tree, and so on.
  2. The STM32CubeMP1 package then takes care of all the Cortex-M4 local configuration (NVIC, MPU, and so on). It can rely on the resource manager to modify system resources without interfering with the Cortex-A7.

3.2.4 Peripheral assignment[edit]

The Cortex-M4 is the Cortex-A7's coprocessor, so it cannot assign peripheral to its usage but it manages all the peripherals assigned to its context.

4 How to go further[edit]

Refer to the Arm website[1] for more detailed information on this core.

5 References[edit]



==<noinclude>{{ApplicableFor
|MPUs list=STM32MP15x
|MPUs checklist=STM32MP13x, STM32MP15x
}}</noinclude>

==Article purpose==
The purpose of this article is to:
* briefly introduce the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 core and its main features
* indicate the level of security supported by this processor

==Peripheral overview==
The Arm Cortex-M4 is seen as a coprocessor on [[STM32MP15 microprocessor | STM32MP15]], where the [[Arm Cortex-A7]] is the main processor that controls it. The Cortex-M4 is present across all the  [[STM32MP15_microprocessor#STM32MP15x_lines | STM32MP15x lines]]. <br />


===Features===
The Cortex-M4 is a 32-bit processor that belongs to the Armv7E-M architecture family. Armv7E-M corresponds to the ARMv7-M architecture, with DSP extension. Among a wide range of features, it includes a memory protection unit (MPU) and a single-precision floating point unit (FPU).

Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features.

===Security support===
The Cortex-M4 '''does not''' support secure mode: it only supports a non-secure mode that defines the Cortex-M4 non-secure [[:Category:STM32_MPU_microprocessor_devices#Hardware_execution_contexts | hardware execution context]].

==Peripheral usage and associated software==

===Boot time===
The [[STM32CubeMP1 architecture | STM32CubeMP1]] package execution startup on the Cortex-M4 coprocessor is controlled by the Cortex-A7, that is running the [[OpenSTLinux architecture overview | OpenSTLinux]] distribution.<br><br>


The coprocessor startup can be done at two different stages of the [[Boot chain overview | boot chain]]:
* by U-Boot SSBL, as explained in the [[How to start the coprocessor from the bootloader]] article
* by [[Linux remoteproc framework overview | Linux remoteproc]], by default

Thanks to a specific  [[OP-TEE_overview | OP-TEE trusted application (TA)]] running on the [[Security_overview | Arm<sup>&reg;</sup> TrustZone]] and to the [[ETZPC_internal_peripheral | ETZPC peripheral]], it is possible to authenticate the Cortex<sup>&reg;</sup>-M4 firmware and install it on isolated MCU RAM to ensure its integrity during the execution. For details, please refer to [[How_to_protect_the_coprocessor_firmware]] article.

===Runtime===

====Overview====
The Cortex-M4 runs the [[STM32CubeMP1 architecture | STM32CubeMP1]] package. <br>
<br>

The Cortex-M4 operates as a coprocessor, either autonomously as any external microcontroller (such as an STM32F4) could, or communicating with the main processor (Cortex-A7) via the [[Linux RPMsg framework overview|RPMsg]] communication pipe.

====Software frameworks====
{{:STM32MP15_internal_peripherals_software_table_template}}
 | Ecosystem
 | [[Arm_Cortex-M4 | Cortex-M4]]
 |
 |
 | [[STM32CubeMP1 architecture | STM32CubeMP1]] package
 |
 |-
 |}

====Peripheral configuration====
The Cortex-M4 configuration is done in two steps:
# As the main processor of the system, the Cortex-A7 (running [[OpenSTLinux architecture overview |OpenSTLinux]] distribution) first takes care of the initialization of all system resources: supplies, clock tree, and so on.
# The [[STM32CubeMP1 architecture | STM32CubeMP1]] package then takes care of all the Cortex-M4 local configuration (NVIC, MPU, and so on). It can rely on the [[Resource_manager_for_coprocessing | resource manager]] to modify system resources without interfering with the Cortex-A7.

====Peripheral assignment====
The Cortex-M4 is the Cortex-A7's coprocessor, so it cannot assign peripheral to its usage but it manages all the peripherals assigned to its context.

==How to go further==
Refer to the Arm website<ref>[https://developer.arm.com/ip-products/processors/cortex-m/cortex-m4 Cortex-M4 processor on Arm developer website]</ref> for more detailed information on this core.

==References==<references/>

<noinclude>

{{ArticleBasedOnModel | Internal peripheral article model}}
[[Category:Arm processors]]
{{PublicationRequestId | 19286 | 2021-03-10 | }}<noinclude>
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<noinclude>{{ApplicableFor
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|MPUs list=STM32MP15x
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|MPUs checklist=STM32MP13x, STM32MP15x
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