Difference between revisions of "DMA internal peripheral"

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Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to:

  • briefly introduce the DMA peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
  • explain, when necessary, how to configure the DMA peripheral.

2 Peripheral overview[edit]

The DMA peripheral is used to perform direct accesses from/to a device or a memory. Each DMA instance supports 8 channels. The selection of the device connected to each DMA channel and controlling the DMA transfers is done via the DMAMUX.

Note: Directly accessing DDR from the DMA is not recommended for high-bandwith or latency-critical transfers. This means that DMA transfers configured by the Arm® Cortex®-A7 operating system, that usually target buffers in external memory, require a hardware mechanism to chain the DMA and a MDMA channel in order to achieve the following flow:

DDR<-> MDMA <-> MCU SRAM <-> DMA <-> device

This feature was already present on STM32H7 microcontroller Series. It is documented in application note AN5001[1].

2.1 Features[edit]

Refer to the STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit]

2.2.1 On STM32MP13x lines More info.png[edit]

DMA1 and DMA2 instances are non-secure peripherals. DMA3 is a secure peripheral.

2.2.2 On STM32MP15x lines More info.png[edit]

DMA1 and DMA2 instances are non-secure peripherals.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The DMA is not used at boot time.

3.2 Runtime[edit]

3.2.1 Overview[edit]

3.2.1.1 On STM32MP13x lines More info.png[edit]

DMA1 and DMA2 can be assigned to the Arm® Cortex®-A7 non-secure context to be controlled in Linux® by the dmaengine framework.
DMA3 can be assigned to the Arm® Cortex®-A7 secure context, to be controlled by a DMA OP-TEE driver, not supported yet by OpenSTLinux.

3.2.1.2 On STM32MP15x lines More info.png[edit]

Each DMA instance can be allocated to:

  • the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the dmaengine framework

or

  • the Arm® Cortex®-M4 to be controlled in STM32Cube MPU Package by the DMA HAL driver

3.2.2 Software frameworks[edit]

3.2.2.1 On STM32MP13x lines More info.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux
Core/DMA DMA OP-TEE DMA driver Linux dmaengine framework
3.2.2.2 On STM32MP15x lines More info.png[edit]

Internal peripherals software table template

|
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Core/DMA
| DMA | | Linux dmaengine framework | STM32Cube DMA driver | |- |}
DMA Linux dmaengine framework STM32Cube DMA driver

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

3.2.4 Peripheral assignment[edit]

3.2.4.1 On STM32MP13x lines More info.png[edit]

Click on the right to expand the legend...

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • ☐ means that the peripheral can be assigned (☑) to the given runtime context.
  • ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE) 		Cortex-A7
non-secure
(Linux)
Core/DMA DMA DMA1 ☐ Assignment (single choice)
DMA2 ☐ Assignment (single choice)
DMA3 ⬚ Assignment (single choice)
3.2.4.2 On STM32MP15x lines More info.png[edit]
Internal peripherals assignment table template 
| rowspan="2" | Core/DMA
| rowspan="2" | DMA
| DMA1
|
| ☐
| ☐
| Assignment (single choice)
|-
| DMA2
|
| ☐
| ☐
| Assignment (single choice)
|-


|}

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • ☐ means that the peripheral can be assigned (☑) to the given runtime context.
  • ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE) 		Cortex-A7
non-secure
(Linux) 		Cortex-M4

(STM32Cube)
Core/DMA DMA DMA1 ☐ ☐ Assignment (single choice)
DMA2 ☐ ☐ Assignment (single choice)

4 References[edit]

  1. ↑ http://www.st.com/resource/en/application_note/dm00360392.pdf 


<noinclude>{{ApplicableFor
|MPUs list=STM32MP13x, STM32MP15x
|MPUs checklist=STM32MP13x,STM32MP15x
}}</noinclude>

==Article purpose==
The purpose of this article is to:
* briefly introduce the DMA peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
* explain, when necessary, how to configure the DMA peripheral.

==Peripheral overview==
The '''DMA''' peripheral is used to perform direct accesses from/to a device or a memory. Each DMA instance supports 8 channels. The selection of the device connected to each DMA channel and controlling the DMA transfers is done via the [[DMAMUX internal peripheral|DMAMUX]].<br /><br />


Note: Directly accessing [[DDRCTRL and DDRPHYC internal peripherals|DDR]] from the DMA is not recommended for high-bandwith or latency-critical transfers. This means that DMA transfers configured by the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 operating system, that usually target buffers in external memory, require a hardware mechanism to chain the DMA and a [[MDMA internal peripheral|MDMA]] channel in order to achieve the following flow:<br />

:DDR<-> MDMA <-> MCU SRAM <-> DMA <-> device <br />

This feature was already present on STM32H7 microcontroller Series. It is documented in application note  AN5001<ref>http://www.st.com/resource/en/application_note/dm00360392.pdf</ref>.

===Features===
Refer to the [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.

===Security support===
===== On {{MicroprocessorDevice | device=13}} =====
DMA1 and DMA2 instances are '''non-secure''' peripherals.
DMA3 is a '''secure''' peripheral.
===== On {{MicroprocessorDevice | device=15}} =====
DMA1 and DMA2 instances are '''non-secure''' peripherals.

==Peripheral usage and associated software==
===Boot time===
The DMA is not used at boot time.

===Runtime===
====Overview====
===== On {{MicroprocessorDevice | device=13}} =====
DMA1 and DMA2 can be assigned to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure context to be controlled in Linux<sup>&reg;</sup> by the [[Dmaengine overview|dmaengine]] framework.<br>

DMA3 can be assigned to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure context, to be controlled by a DMA [[OP-TEE overview|OP-TEE]] driver, not supported yet by OpenSTLinux.

===== On {{MicroprocessorDevice | device=15}} =====
Each DMA instance can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by the [[Dmaengine overview|dmaengine]] framework
or
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be controlled in STM32Cube MPU Package by the [[STM32CubeMP1 architecture|DMA HAL driver]]

====Software frameworks====
===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13 internal_peripherals_software_table_template}}
 | Core/DMA
 | [[DMA internal peripheral|DMA]]
 | [[OP-TEE_overview|OP-TEE DMA driver]]
 | [[Dmaengine overview|Linux dmaengine framework]]
 |
 |-
 |}
===== On {{MicroprocessorDevice | device=15}} =====
{{:Internal_STM32MP15_internal_peripherals_software_table_template}}
 | Core/DMA
 | [[DMA internal peripheral|DMA]]
 | 
 | [[Dmaengine overview|Linux dmaengine framework]]
 | [[STM32CubeMP1 architecture|STM32Cube DMA driver]]
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

====Peripheral assignment====
===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13 internal_peripherals_assignment_table_template}}<section begin=stm32mp13 />

 | rowspan="3" | Core/DMA
 | rowspan="3" | [[DMA internal peripheral|DMA]]
 | DMA1
 |
 | <span title="assignable peripheral" style="font-size:21px">☐</span>

 | Assignment (single choice)
 |-
 | DMA2
 |
 | <span title="assignable peripheral" style="font-size:21px">☐</span>

 | Assignment (single choice)
 |-
 | DMA3
 | <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>

 |
 | Assignment (single choice)
 |-<section end=stm32mp13 />

 |}
===== On {{MicroprocessorDevice | device=15}} =====
{{:Internal_STM32MP15_internal_peripherals_assignment_table_template}}<section begin=stm32mp15 />

 | rowspan="2" | Core/DMA
 | rowspan="2" | [[DMA internal peripheral|DMA]]
 | DMA1
 |
 | <span title="assignable peripheral" style="font-size:21px">☐</span>

 | <span title="assignable peripheral" style="font-size:21px">☐</span>

 | Assignment (single choice)
 |-
 | DMA2
 |
 | <span title="assignable peripheral" style="font-size:21px">☐</span>

 | <span title="assignable peripheral" style="font-size:21px">☐</span>

 | Assignment (single choice)
 |-<section end=stm32mp15 />

 |}

==References==<references/>

<noinclude>

[[Category:DMA peripherals]]
{{PublicationRequestId | 9109 | 2018-10-10 | AnneJ}}
{{ArticleBasedOnModel| Internal peripheral article model}}</noinclude>
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  |}
 
===== On {{MicroprocessorDevice | device=15}} =====
  
===== On {{MicroprocessorDevice | device=15}} =====
−
{{:Internal_peripherals_software_table_template}}
 +
{{:STM32MP15_internal_peripherals_software_table_template}}
 
  | Core/DMA
  
  | Core/DMA
 
  | [[DMA internal peripheral|DMA]]
  
  | [[DMA internal peripheral|DMA]]
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  |}
 
===== On {{MicroprocessorDevice | device=15}} =====
  
===== On {{MicroprocessorDevice | device=15}} =====
−
{{:Internal_peripherals_assignment_table_template}}
 +
{{:STM32MP15_internal_peripherals_assignment_table_template}}
 
<section begin=stm32mp15 />
  
<section begin=stm32mp15 />
 
  | rowspan="2" | Core/DMA
  
  | rowspan="2" | Core/DMA
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