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Difference between revisions of "TZC internal peripheral"
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Contents
1 Article purpose[edit]
The purpose of this article is to:
- briefly introduce the TZC peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how it can be allocated to the three runtime contexts and linked to the corresponding software components
- explain, when necessary, how to configure the TZC peripheral.
2 Peripheral overview[edit]
The TZC peripheral is used to filter read/write accesses to the DDR controller according to TrustZone access rights, and according to Non-Secure master Address ID (NSAID) on up to 9 programmable regions.
2.1 Features[edit]
Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.
2.2 Security support[edit]
The TZC is a secure peripheral.
3 Peripheral usage and associated software[edit]
3.1 Boot time[edit]
The TZC is configured at boot time to setup DDR accesses.
3.2 Runtime[edit]
3.2.1 Overview[edit]
The TZC is a system peripheral and is controlled by the Arm® Cortex®-A7 secure.
3.2.2 Software frameworks[edit]
Internal peripherals software table template
| Security | TZC | OP-TEE TZC driver | | | |- |}
3.2.3 Peripheral configuration[edit]
The configuration is applied by the firmware running in the secure context.
This configuration is done in TF-A or in OP-TEE.
3.2.4 Peripheral assignment[edit]
Internal peripherals assignment table template
| rowspan="1" | Security | rowspan="1" | TZC | TZC | ✓ | | | |-
|}
4 How to go further[edit]
The TZC is an Arm® peripheral: TZC-400 TrustZone Address Space Controller[1]
5 References[edit]
<noinclude> {{ArticleBasedOnModel| [[Internal peripheral article model]]}} {{ArticleMainWriter|YannG}} {{ArticleApprovedVersion | YannG | Jean-ChristopheT | YannG - 19Sept'18 | AlainF - 19Sept'18 - 8790 | 07Jan’19}} [[Category:Security peripherals]]</noinclude> ==Article purpose== The purpose of this article is to: * briefly introduce the TZC peripheral and its main features * indicate the level of security supported by this hardware block * explain how it can be allocated to the three runtime contexts and linked to the corresponding software components * explain, when necessary, how to configure the TZC peripheral. ==Peripheral overview== The TZC peripheral is used to filter read/write accesses to the DDR controller according to TrustZone access rights, and according to Non-Secure master Address ID (NSAID) on up to 9 programmable regions.<br /> ===Features=== Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented. ===Security support=== The TZC is a '''secure''' peripheral. ==Peripheral usage and associated software== ===Boot time=== The TZC is configured at boot time to setup DDR accesses. ===Runtime=== ====Overview==== The TZC is a system peripheral and is controlled by the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 secure. ====Software frameworks==== {{:Internal_peripherals_software_table_template}} | Security | [[TZC internal peripheral|TZC]] | [[OP-TEE_overview|OP-TEE TZC driver]] | | | |- |} ====Peripheral configuration==== The configuration is applied by the firmware running in the secure context. This configuration is done in [[TF-A_overview|TF-A]] or in [[OP-TEE_overview|OP-TEE]]. ====Peripheral assignment==== {{:Internal_peripherals_assignment_table_template}}<onlyinclude> | rowspan="1" | Security | rowspan="1" | [[TZC internal peripheral|TZC]] | TZC | <span title="system peripheral" style="font-size:21px">✓</span> | | | |-</onlyinclude> |} ==How to go further== The TZC is an Arm<sup>®</sup> peripheral: TZC-400 TrustZone Address Space Controller<ref>http://infocenter.arm.com/help/topic/com.arm.doc.ddi0504c/DDI0504C_tzc400_r0p1_trm.pdf</ref> ==References==<references/> <noinclude> [[Category:Security peripherals]] {{PublicationRequestId | 8790 | 2018-09-19 | AlainF}} {{ArticleBasedOnModel| Internal peripheral article model}}</noinclude>
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==References== |
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| + | {{PublicationRequestId | 8790 | 2018-09-19 | AlainF}} |
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| + | {{ArticleBasedOnModel| Internal peripheral article model}} |
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| + | </noinclude> |
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