Registered User mNo edit summary |
Registered User Tag: 2017 source edit |
||
(69 intermediate revisions by 9 users not shown) | |||
Line 1: | Line 1: | ||
{{ApplicableFor | |||
|MPUs list=STM32MP13x, STM32MP15x | |MPUs list=STM32MP13x, STM32MP15x, STM32MP21x, STM32MP23x, STM32MP25x | ||
|MPUs checklist=STM32MP13x,STM32MP15x | |MPUs checklist=STM32MP13x, STM32MP15x, STM32MP21x, STM32MP23x, STM32MP25x | ||
}} | }} | ||
==Article purpose== | |||
The purpose of this article is to: | |||
* briefly introduce the TAMP peripheral and its main features, | |||
* indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts), | |||
* list the software frameworks and drivers managing the peripheral, | |||
* explain how to configure the peripheral. | |||
{| | ==Peripheral overview== | ||
The TAMP peripheral is a '''secure''' peripheral. | |||
The '''TAMP''' peripheral is used to prevent any attempt by an attacker to perform an unauthorized physical or electronic action against the device. It also includes the backup registers that remain powered-on when the platform is switched off.<br /> | |||
The '''TAMP''' peripheral control the access to the backup registers. | |||
It is important to notice that a tamper event can erase the following secrets: | |||
* On {{MicroprocessorDevice | device=13}} | |||
** the [[STM32MP13 backup registers|backup registers]] | |||
** the [[STM32MP13_SRAM_internal_memory|SRAM3]] | |||
** the [[BKPSRAM internal memory]] | |||
** the [[BSEC_internal_peripheral|OTP upper fuses]] are forced to 0 and [[BSEC_internal_peripheral|BSEC]] mode switch to OTP-INVALID. | |||
* On {{MicroprocessorDevice | device=15}} | |||
** the [[STM32MP15 backup registers|backup registers]] | |||
** the [[BKPSRAM internal memory]] | |||
* On {{MicroprocessorDevice | device=21}} | |||
** the [[STM32MP2 backup registers | backup registers ]] | |||
** the [[STM32MP2_SRAM_internal_memory|SRAM1]] | |||
** the [[SAES internal peripheral | SAES]], [[CRYP internal peripheral | CRYP1/2]], [[HASH internal peripheral | HASH1/2]] peripherals when POTTAMPRESETMASK = 0 in [[SYSCFG_internal_peripheral|SYSCFG]] | |||
** [[PKA internal peripheral | PKA]] SRAM | |||
** the [[BSEC_internal_peripheral|OTP upper fuses]] are forced to 0 and [[BSEC_internal_peripheral|BSEC]] mode switch to OTP-INVALID. | |||
** the [[BKPSRAM internal memory]] | |||
* On {{MicroprocessorDevice | device=25}} and {{MicroprocessorDevice | device=23}} | |||
** the [[STM32MP2 backup registers | backup registers ]] | |||
** the [[STM32MP2_SRAM_internal_memory|SRAM1]] | |||
** the [[SAES internal peripheral | SAES]], [[CRYP internal peripheral | CRYP1/2]], [[HASH internal peripheral | HASH]], [[OTFDEC internal peripheral | OTFDEC]] peripherals when POTTAMPRESETMASK = 0 in [[SYSCFG_internal_peripheral|SYSCFG]] | |||
** [[PKA internal peripheral | PKA]] SRAM | |||
** the [[BSEC_internal_peripheral|OTP upper fuses]] are forced to 0 and [[BSEC_internal_peripheral|BSEC]] mode switch to OTP-INVALID. | |||
** the [[BKPSRAM internal memory]] | |||
Refer to the [[STM32 MPU resources#Reference manuals|STM32 MPU reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented. | |||
{{Info | On {{MicroprocessorDevice | device=2}}, TAMP is a [[Resource Isolation Framework overview|RIF]]-Aware peripheral}} | |||
==Peripheral usage== | |||
This chapter is applicable in the scope of the '''OpenSTLinux BSP''' running on the Arm<sup>®</sup> Cortex<sup>®</sup>-A processor(s), and the '''FwST-M Package''' running on the Arm<sup>®</sup> Cortex<sup>®</sup>-M processor. | |||
===Boot time assignment=== | |||
The TAMP is used at boot time to share data between the ROM code, FSBL and SSBL: see [[STM32MP13 backup registers|STM32MP13 backup registers]], [[STM32MP15 backup registers|STM32MP15 backup registers]] or [[STM32MP2 backup registers|STM32MP2 backup registers]] for further information. | |||
====On {{MicroprocessorDevice | device=1}}==== | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}} | |||
<section begin=stm32mp13_boottime /><section begin=stm32mp15_boottime /> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral|TAMP]] | |||
| TAMP | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
|- | |||
<section end=stm32mp13_boottime /><section end=stm32mp15_boottime /> | |||
|} | |||
====On {{MicroprocessorDevice | device=2}}==== | |||
=====For {{TrustedDomainFlavor|flavor=A35-TD}}===== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}} | |||
<section begin=stm32mp21_a35_boottime/><section begin=stm32mp23_a35_boottime/><section begin=stm32mp25_a35_boottime/> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral | TAMP]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| TAMP | |||
| colspan="3" text-align:center;| Shareable at internal peripheral level thanks to the RIF: see the [[TAMP internal peripheral#stm32mp2_TAMP_a35_boottime_rif | boot time allocation per feature]] | |||
| | |||
|- | |||
<section end=stm32mp21_a35_boottime/><section end=stm32mp23_a35_boottime/><section end=stm32mp25_a35_boottime/> | |||
|} | |||
<span id="stm32mp2_TAMP_a35_boottime_rif"></span>The below table shows the possible boot time allocations for the features of the TAMP instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime_rif}} | |||
| TAMP resource 0 | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| TAMP resource 1 | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
|- | |||
| TAMP resource 2 | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
|} | |||
=====For {{TrustedDomainFlavor|flavor=M33-TD}}===== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_m33_boottime}} | |||
<section begin=stm32mp21_m33_boottime/><section begin=stm32mp23_m33_boottime/><section begin=stm32mp25_m33_boottime/> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral | TAMP]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| TAMP | |||
| colspan="4" text-align:center;| Shareable at internal peripheral level thanks to the RIF: see the [[TAMP internal peripheral#stm32mp2_TAMP_m33_boottime_rif | boot time allocation per feature]] | |||
| | |||
|- | |||
<section end=stm32mp21_m33_boottime/><section end=stm32mp23_m33_boottime/><section end=stm32mp25_m33_boottime/> | |||
|} | |||
<span id="stm32mp2_TAMP_m33_boottime_rif"/>The below table shows the possible boot time allocations for the features of the TAMP instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_m33_boottime_rif}} | |||
| TAMP resource 0 | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| TAMP resource 1 | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
|- | |||
| TAMP resource 2 | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |||
===Runtime assignment=== | |||
TAMP is seen as a system peripheral. The tamper detection and management is, after configuration, non modifiable. | |||
TAMP is configured in OP-TEE to manage tamper events. | |||
====On {{MicroprocessorDevice | device=13}}==== | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp13_runtime}} | |||
<section begin=stm32mp13_runtime /> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral|TAMP]] | |||
| TAMP | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
|- | |||
<section end=stm32mp13_runtime /> | |||
|} | |||
====On {{MicroprocessorDevice | device=15}}==== | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp15_runtime}} | |||
<section begin=stm32mp15_runtime /> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral|TAMP]] | |||
| TAMP | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
<section end=stm32mp15_runtime /> | |||
|} | |||
====On {{MicroprocessorDevice | device=21}}==== | |||
=====For {{TrustedDomainFlavor|flavor=A35-TD}}===== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp21_runtime}} | |||
<section begin=stm32mp21_a35_runtime /> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral | TAMP]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| TAMP | |||
| colspan="4" text-align:center;| Shareable at internal peripheral level thanks to the RIF: see the [[TAMP internal peripheral#stm32mp21_TAMP_a35_runtime_rif | runtime allocation per feature]] | |||
| | |||
|- | |||
<section end=stm32mp21_a35_runtime /> | |||
|} | |||
<span id="stm32mp21_TAMP_a35_runtime_rif"/>The below table shows the possible runtime allocations for the features of the TAMP instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp21_runtime_rif}} | |||
| TAMP resource 0 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| TAMP resource 1 | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| TAMP resource 2 | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
|} | |||
=====For {{TrustedDomainFlavor|flavor=M33-TD}}===== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp21_runtime}} | |||
<section begin=stm32mp21_m33_runtime /> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral | TAMP]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| TAMP | |||
| colspan="4" text-align:center;| Shareable at internal peripheral level thanks to the RIF: see the [[TAMP internal peripheral#stm32mp21_TAMP_m33_runtime_rif | runtime allocation per feature]] | |||
| | |||
|- | |||
<section end=stm32mp21_m33_runtime /> | |||
|} | |||
<span id="stm32mp21_TAMP_m33_runtime_rif"/>The below table shows the possible runtime allocations for the features of the TAMP instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp21_runtime_rif}} | |||
| TAMP resource 0 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| TAMP resource 1 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| TAMP resource 2 | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=23}} ==== | |||
=====For {{TrustedDomainFlavor|flavor=A35-TD}}===== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp23_runtime}} | |||
<section begin=stm32mp23_a35_runtime /> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral | TAMP]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| TAMP | |||
| colspan="4" text-align:center;| Shareable at internal peripheral level thanks to the RIF: see the [[TAMP internal peripheral#stm32mp23_TAMP_a35_runtime_rif | runtime allocation per feature]] | |||
| | |||
|- | |||
<section end=stm32mp23_a35_runtime /> | |||
|} | |||
<span id="stm32mp23_TAMP_a35_runtime_rif"/>The below table shows the possible runtime allocations for the features of the TAMP instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp23_runtime_rif}} | |||
| TAMP resource 0 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| TAMP resource 1 | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| TAMP resource 2 | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
|} | |||
=====For {{TrustedDomainFlavor|flavor=M33-TD}}===== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp23_runtime}} | |||
<section begin=stm32mp23_m33_runtime /> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral | TAMP]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| TAMP | |||
| colspan="4" text-align:center;| Shareable at internal peripheral level thanks to the RIF: see the [[TAMP internal peripheral#stm32mp23_TAMP_m33_runtime_rif | runtime allocation per feature]] | |||
| | |||
|- | |||
<section end=stm32mp23_m33_runtime /> | |||
|} | |||
<span id="stm32mp23_TAMP_m33_runtime_rif"/>The below table shows the possible runtime allocations for the features of the TAMP instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp23_runtime_rif}} | |||
| TAMP resource 0 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| TAMP resource 1 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| TAMP resource 2 | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=25}}==== | |||
=====For {{TrustedDomainFlavor|flavor=A35-TD}}===== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime}} | |||
<section begin=stm32mp25_a35_runtime /> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral | TAMP]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| TAMP | |||
| colspan="5" text-align:center;| Shareable at internal peripheral level thanks to the RIF: see the [[TAMP internal peripheral#stm32mp25_TAMP_a35_runtime_rif | runtime allocation per feature]] | |||
| | |||
|- | |||
<section end=stm32mp25_a35_runtime /> | |||
|} | |||
<span id="stm32mp25_TAMP_a35_runtime_rif"/>The below table shows the possible runtime allocations for the features of the TAMP instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime_rif}} | |||
| TAMP resource 0 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| TAMP resource 1 | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
|- | |||
| TAMP resource 2 | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
|- | |||
|} | |||
=====For {{TrustedDomainFlavor|flavor=M33-TD}}===== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime}} | |||
<section begin=stm32mp25_m33_runtime /> | |||
| rowspan="1" | Security | |||
| rowspan="1" | [[TAMP internal peripheral | TAMP]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| TAMP | |||
| colspan="5" text-align:center;| Shareable at internal peripheral level thanks to the RIF: see the [[TAMP internal peripheral#stm32mp25_TAMP_m33_runtime_rif | runtime allocation per feature]] | |||
| | |||
|- | |||
<section end=stm32mp25_m33_runtime /> | |||
|} | |||
<span id="stm32mp25_TAMP_m33_runtime_rif"/>The below table shows the possible runtime allocations for the features of the TAMP instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime_rif}} | |||
| TAMP resource 0 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |- | ||
| TAMP resource 1 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
|- | |- | ||
| | | TAMP resource 2 | ||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
|- | |- | ||
|} | |} | ||
==Software frameworks and drivers== | |||
Below are listed the software frameworks and drivers managing the TAMP peripheral for the embedded software components listed in the above tables. | |||
* '''Linux<sup>®</sup>''': | |||
** syscon driver ({{CodeSource | Linux kernel | drivers/mfd/syscon.c}}) based on binding {{CodeSource | Linux kernel | Documentation/devicetree/bindings/mfd/syscon.yaml | syscon.yaml }} | |||
** [[NVMEM_overview|NVMEM framework]] for TAMP Backup Register access (using {{CodeSource | Linux kernel | drivers/nvmem/stm32-tamp-nvram.c| TAMP Backup Register Driver}}).<br>For details on Backup register usage see [[TAMP_device_tree_configuration#How_to_use_TAMP_Backup_Registers|How to use TAMP Backup Registers]] | |||
* '''OP-TEE''': {{CodeSource | OP-TEE_OS | core/drivers/stm32_tamp.c | TAMP driver}} and {{CodeSource | OP-TEE_OS | core/include/drivers/stm32_tamp.h | header file of TAMP OP-TEE driver}} + {{CodeSource | OP-TEE_OS | core/drivers/nvmem/stm32_tamp_nvram.c | TAMP NVRAM driver using NVMEM API}} | |||
* '''TF-A BL2''': {{CodeSource | TF-A | plat/st/stm32mp1/bl2_plat_setup.c | TF-A backup register access}} | |||
* '''U-Boot''': {{CodeSource | U-Boot | include/nvmem.h |U-Boot backup register access using NVMEM API}} | |||
* '''TF-M''': {{CodeSource | TF-M | platform/ext/target/stm/common/stm32mp2xx/native_driver/src/tamper/stm32_tamp.c | TF-M backup register access}} | |||
==How to assign and configure the peripheral== | |||
The peripheral assignment can be done via the [[STM32CubeMX]] graphical tool (and manually completed if needed).<br /> | |||
This tool also helps to configure the peripheral: | |||
* partial device trees (pin control and clock tree) generation for the OpenSTLinux software components, | |||
* HAL initialization code generation for the STM32CubeMPU Package. | |||
The configuration is applied by the firmware running in the context in which the peripheral is assigned. | |||
For the Linux kernel configuration, sysconf part, please refer to [[TAMP device tree configuration]].<br> | |||
For the secure configuration, please refer to [[TAMP device tree configuration]] and [[Tamper_configuration|Tamper configuration]]. | |||
==References== | |||
<references/> | |||
<noinclude> | <noinclude> | ||
[[Category:Security peripherals]] | [[Category:Security peripherals]] | ||
{{ArticleBasedOnModel | Internal peripheral article model}} | |||
{{PublicationRequestId | 8792 | 2018-10-01}} | |||
{{ToBeReviewedByTW}} | |||
</noinclude> | </noinclude> |
Latest revision as of 11:20, 2 July 2025
1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the TAMP peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The TAMP peripheral is a secure peripheral.
The TAMP peripheral is used to prevent any attempt by an attacker to perform an unauthorized physical or electronic action against the device. It also includes the backup registers that remain powered-on when the platform is switched off.
The TAMP peripheral control the access to the backup registers.
It is important to notice that a tamper event can erase the following secrets:
- On STM32MP13x lines
- the backup registers
- the SRAM3
- the BKPSRAM internal memory
- the OTP upper fuses are forced to 0 and BSEC mode switch to OTP-INVALID.
- On STM32MP15x lines
- On STM32MP21x lines
- the backup registers
- the SRAM1
- the SAES, CRYP1/2, HASH1/2 peripherals when POTTAMPRESETMASK = 0 in SYSCFG
- PKA SRAM
- the OTP upper fuses are forced to 0 and BSEC mode switch to OTP-INVALID.
- the BKPSRAM internal memory
- On STM32MP25x lines
and STM32MP23x lines
- the backup registers
- the SRAM1
- the SAES, CRYP1/2, HASH, OTFDEC peripherals when POTTAMPRESETMASK = 0 in SYSCFG
- PKA SRAM
- the OTP upper fuses are forced to 0 and BSEC mode switch to OTP-INVALID.
- the BKPSRAM internal memory
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
![]() |
On STM32MP2 series, TAMP is a RIF-Aware peripheral |
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the FwST-M Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
The TAMP is used at boot time to share data between the ROM code, FSBL and SSBL: see STM32MP13 backup registers, STM32MP15 backup registers or STM32MP2 backup registers for further information.
3.1.1. On STM32MP1 series[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 nonsecure (U-Boot) | |||
Security | TAMP | TAMP | ✓ | ☑ | ☑ |
3.1.2. On STM32MP2 series[edit | edit source]
3.1.2.1. For A35-TD flavor
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Security | TAMP ![]() |
TAMP | Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature |
The below table shows the possible boot time allocations for the features of the TAMP instance.
Feature | Boot time allocation ![]() |
Comment | ||
---|---|---|---|---|
Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | ||
TAMP resource 0 | ⬚ | ⬚ | ||
TAMP resource 1 | ✓ | ☑ | ☑ | |
TAMP resource 2 | ⬚ | ⬚ |
3.1.2.2. For M33-TD flavor
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) |
Cortex-M33 secure (MCUboot) | |||
Security | TAMP ![]() |
TAMP | Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature |
The below table shows the possible boot time allocations for the features of the TAMP instance.
Feature | Boot time allocation ![]() |
Comment | |||
---|---|---|---|---|---|
Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) |
Cortex-M33 secure (MCUboot) | ||
TAMP resource 0 | ⬚ | ⬚ | ☐ | ||
TAMP resource 1 | ✓ | ☑ | ☑ | ☑ | |
TAMP resource 2 | ⬚ | ⬚ | ☐ |
3.2. Runtime assignment[edit | edit source]
TAMP is seen as a system peripheral. The tamper detection and management is, after configuration, non modifiable. TAMP is configured in OP-TEE to manage tamper events.
3.2.1. On STM32MP13x lines
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | ||
---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 nonsecure (Linux) | |||
Security | TAMP | TAMP | ☑ | ☑ |
3.2.2. On STM32MP15x lines
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 nonsecure (Linux) |
Cortex-M4 (STM32Cube) | |||
Security | TAMP | TAMP | ☑ | ☑ | ☐ |
3.2.3. On STM32MP21x lines
[edit | edit source]
3.2.3.1. For A35-TD flavor
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Security | TAMP ![]() |
TAMP | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the TAMP instance.
Feature | Runtime allocation ![]() |
Comment | |||
---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | ||
TAMP resource 0 | ☐OP-TEE | ⬚ | ☐ | ☐ | |
TAMP resource 1 | ✓OP-TEE ✓TF-A BL31 |
⬚ | ⬚ | ⬚ | |
TAMP resource 2 | ⬚OP-TEE | ⬚ | ✓ | ⬚ |
3.2.3.2. For M33-TD flavor
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Security | TAMP ![]() |
TAMP | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the TAMP instance.
Feature | Runtime allocation ![]() |
Comment | |||
---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | ||
TAMP resource 0 | ☐OP-TEE ⬚TF-A BL31 |
⬚ | ☐ | ☐ | |
TAMP resource 1 | ☐OP-TEE ☐TF-A BL31 |
⬚ | ⬚ | ⬚ | |
TAMP resource 2 | ⬚OP-TEE ⬚TF-A BL31 |
⬚ | ✓ | ⬚ |
3.2.4. On STM32MP23x lines
[edit | edit source]
3.2.4.1. For A35-TD flavor
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Security | TAMP ![]() |
TAMP | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the TAMP instance.
Feature | Runtime allocation ![]() |
Comment | |||
---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | ||
TAMP resource 0 | ☐OP-TEE | ⬚ | ☐ | ☐ | |
TAMP resource 1 | ✓OP-TEE ✓TF-A BL31 |
⬚ | ⬚ | ⬚ | |
TAMP resource 2 | ⬚OP-TEE | ⬚ | ✓ | ⬚ |
3.2.4.2. For M33-TD flavor
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Security | TAMP ![]() |
TAMP | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the TAMP instance.
Feature | Runtime allocation ![]() |
Comment | |||
---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | ||
TAMP resource 0 | ☐OP-TEE ⬚TF-A BL31 |
⬚ | ☐ | ☐ | |
TAMP resource 1 | ☐OP-TEE ☐TF-A BL31 |
⬚ | ⬚ | ⬚ | |
TAMP resource 2 | ⬚OP-TEE ⬚TF-A BL31 |
⬚ | ✓ | ⬚ |
3.2.5. On STM32MP25x lines
[edit | edit source]
3.2.5.1. For A35-TD flavor
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | |||||
---|---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
Security | TAMP ![]() |
TAMP | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the TAMP instance.
Feature | Runtime allocation ![]() |
Comment | ||||
---|---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | ||
TAMP resource 0 | ☐OP-TEE | ⬚ | ☐ | ☐ | ☐ | |
TAMP resource 1 | ✓OP-TEE ✓TF-A BL31 |
⬚ | ⬚ | ⬚ | ||
TAMP resource 2 | ⬚OP-TEE | ⬚ | ✓ | ⬚ |
3.2.5.2. For M33-TD flavor
[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | |||||
---|---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
Security | TAMP ![]() |
TAMP | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the TAMP instance.
Feature | Runtime allocation ![]() |
Comment | ||||
---|---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | ||
TAMP resource 0 | ☐OP-TEE ⬚TF-A BL31 |
⬚ | ☐ | ☐ | ☐ | |
TAMP resource 1 | ☐OP-TEE ☐TF-A BL31 |
⬚ | ⬚ | ⬚ | ||
TAMP resource 2 | ⬚OP-TEE ⬚TF-A BL31 |
⬚ | ✓ | ⬚ |
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers managing the TAMP peripheral for the embedded software components listed in the above tables.
- Linux®:
- syscon driver (drivers/mfd/syscon.c ) based on binding syscon.yaml
- NVMEM framework for TAMP Backup Register access (using TAMP Backup Register Driver ).
For details on Backup register usage see How to use TAMP Backup Registers
- OP-TEE: TAMP driver and header file of TAMP OP-TEE driver + TAMP NVRAM driver using NVMEM API
- TF-A BL2: TF-A backup register access
- U-Boot: U-Boot backup register access using NVMEM API
- TF-M: TF-M backup register access
5. How to assign and configure the peripheral[edit | edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
For the Linux kernel configuration, sysconf part, please refer to TAMP device tree configuration.
For the secure configuration, please refer to TAMP device tree configuration and Tamper configuration.
6. References[edit | edit source]