STM32MP1 DMA

Revision as of 15:38, 1 February 2023 by Registered User (→‎STM32MP15 DMA topology)
Applicable for STM32MP15x lines


1. Article purpose[edit source]

The purpose of this article is to explain STM32MP15 DMA topology and the associated configurations recommended by ST.

2. STM32MP15 DMA topology[edit source]

STM32MP15 owns 3 DMA instances:

  • 1 MDMA internal peripheral dedicated to transfers between some internal peripherals and external memories (DDR) and between internal and external memories.
  • 2 DMA internal peripheral (DMA1/DMA2) dedicated to transfers between internal peripherals and internal SRAM. These two DMA instances are coupled with a DMAMUX internal peripheral in charge of routing internal peripheral requests to DMA channels.
Info white.png Information
Transfers between internal peripherals and DDR, via DMA1/DMA2, are possible but not recommended for high-bandwith or latency-critical transfers

The following figures show the different DMA configuration available on STM32MP1 and the associated request and data connections.

  • Internal peripherals - internal SRAM with DMA transfer
DMA transfer.png
In this configuration, the data flow is:
  • peripheral to memory direction: data are directly transferred from peripheral to final internal RAM buffer by DMA.
  • memory to peripheral direction: data are transferred from original internal SRAM buffer to peripheral by DMA.
  • Internal peripherals - DDR with MDMA transfer
MDMA transfer.png
In this configuration, the data flow is:
  • peripheral to memory direction: data are directly transferred from peripheral to final DDR buffer by MDMA.
  • memory to peripheral direction: data are transferred from original DDR buffer to peripheral by MDMA.


  • Internal peripherals - DDR with DMA - MDMA chained transfer
File:DMA MDAM transfer.png
In this configuration, the data flow is:
  • peripheral to memory direction: data are transferred from peripheral to temporary internal SRAM buffer by DMA then from temporary internal SRAM buffer to DDR buffer by MDMA.
  • memory to peripheral direction: data are transferred from DDR buffer to temporary internal SRAM buffer by MDMA, then from temporary internal SRAM buffer to peripheral by DMA.

For more information about the DMA controllers above and to know the DMA configuration that should be used with each internal peripheral, please refer to STM32MP15 reference manuals.

3. ST recommandations[edit source]

3.1. For Cortex-M4 execution context[edit source]

Cortex-M4 accesses by default internal SRAM for code and data.
In this context, DMA transfers will operate only between peripheral and internal SRAM.
That's why ST recommends to dedicate one DMA internal peripheral to Cortex-M4.

3.2. For Cortex-A7 secure execution context[edit source]

Cortex-A7 secure firmware is located in SYSRAM (both code and data). As the internal peripherals and the SYSRAM associated to the Cortex-A7 secure context are also secure, the MDMA must be used to support transfers between them because it is secure aware.

3.3. Cortex-A7 non-secure execution context[edit source]

Cortex-A7 non-secure firmware is mainly located in external memory (DDR). In consequence, DMA transfers will operate between peripherals and DDR. But as the different internal peripherals don't have the same requirements in term of bandwidth, real time and flow control, customer will have to use one of the three DMA configuration described in STM32MP15 DMA topology. To ease the selection, the following table sums up possible choices for each peripheral and highlight the recommended configuration. Note that this configuration is set by default in device tree (dtsi).

Peripheral no DMA mode DMA mode MDMA mode DMA-MDMA chaining mode Default mode
U(S)ART Yes Yes No Yes no DMA mode
ADC Yes Yes No Yes DMA-MDMA chaining mode
SPI Yes Yes Yes Only instance 6 No DMA or MDMA mode depending on instance
SPDIFRx No Yes No No DMA mode
SAI No Yes No No DMA mode
I2C Yes Yes Yes Only instances 4 and 6 No DMA or MDMA mode depending on instance
Timer Yes Yes No Yes DMA-MDMA chaining mode
DFSDM Yes Yes No No DMA mode
I2S No Yes No No DMA mode
DCMI No No No Yes DMA-MDMA chaining mode
FMC No No Yes No MDMA mode
QUADSPI No No Yes No MDMA mode
HASH No No Yes No MDMA mode
CRYP No No Yes No MDMA mode


4. ST reference boards default configuration[edit source]

4.1. STM32MP15 Evaluation board DMA configuration[edit source]

The following table provides the list of the peripherals for which DMA is configured. Associated configurations are also described.

Peripheral Request line DMA mode
CRYP1 in MDMA mode
out
DCMI tx DMA-MDMA chaining mode
DFSDM channel 0 - rx DMA mode
channel 1 - rx
channel 2 - rx
channel 3 - rx
HASH1 in MDMA mode
I2S2 rx DMA mode
tx
SAI2 a - tx DMA mode
b - rx
USART2 rx DMA mode
tx

4.2. STM32MP15 Discovery kit DMA configuration[edit source]

The following table provides the list of the peripherals for which DMA is configured. Associated configurations are also described

Peripheral Request line DMA mode
ADC1 rx DMA-MDMA chaining mode
ADC2 rx DMA-MDMA chaining mode
CRYP1 in MDMA mode
out
HASH1 in MDMA mode
I2S2 rx DMA mode
tx
SAI2 a - tx DMA mode
b - rx
USART2 rx DMA mode
tx

Direct memory access

Doubledata rate (memory domain)

Random access memory (Early computer memories generally hadserial access. Memories where any given address can be accessed when desired were then called "random access" to distinguish them from the memories where contents can only be accessed in a fixed order. The term is used today for volatile random-acces ssemiconductor memories.)

Cortex®

Digital Camera memory interface

Digital filter for sigma-delta modulator

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