Difference between revisions of "STM32MP15 DMA"

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1 Article purpose[edit]

The purpose of this article is to explain STM32MP15 DMA topology and the associated configurations recommended by ST.

2 STM32MP15 DMA topology[edit]

STM32MP15 owns 3 DMA instances:

  • 1 MDMA internal peripheral dedicated to transfers between some internal peripherals and external memories (DDR) and between internal and external memories.
  • 2 DMA internal peripheral (DMA1/DMA2) dedicated to transfers between internal peripherals and internal SRAM. These two DMA instances are coupled with a DMAMUX internal peripheral in charge of routing internal peripheral requests to DMA channels.
Info.png Transfers between internal peripherals and DDR, via DMA1/DMA2, are possible but not recommended for high-bandwith or latency-critical transfers

The following figures show the different DMA configuration available on STM32MP1 and the associated request and data connections.

For more information about the DMA controllers above and to know the DMA configuration that should be used with each internal peripheral, please refer to STM32MP15 reference manuals.

3 ST Recommandations[edit]

3.1 For Cortex-M4 execution context[edit]

Cortex-M4 access by default internal SRAM for code and data.
In this context, DMA transfers will operate only between peripheral and internal SRAM.
That's why ST recommends to dedicate one DMA internal peripheral to Cortex-M4.

3.2 For Cortex-A7 secure execution context[edit]

Cortex-A7 secure firmware is located in SYSRAM (both code and data). As the internal peripherals and the SYSRAM associated to the Cortex-A7 secure context are also secure, the MDMA must be used to support transfers between them because it is secure aware.

3.3 Cortex-A7 non-secure execution context[edit]

Cortex-A7 non-secure firmware is mainly located in external memory (DDR). In consequence, DMA transfers will operate between peripherals and DDR. But as the different internal peripherals don't have the same requirements in term of bandwidth, real time and flow control, customer will have to use one of the three DMA configuration described in STM32MP15 DMA topology. To ease the selection, the following table sums up possible choices for each peripheral and highlight the recommended configuration. Note that this configuration is set by default in STM32MP15 device tree (dtsi).


4 ST reference boards default configuration[edit] 

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{{ArticleMainWriter|GeraldB}}
{{ArticleApprovedVersion | Jean-ChristopheT | Nobody | No previous approved version | Automatic approval (article under construction) | 19Feb’19}}__FORCETOC__

== Article purpose ==
The purpose of this article is to explain STM32MP15 DMA topology and the associated configurations recommended by ST.

== STM32MP15 DMA topology==
STM32MP15 owns 3 DMA instances:
* 1 [[MDMA internal peripheral]] dedicated to transfers between some internal peripherals and external memories (DDR) and between internal and external memories.
* 2 [[DMA internal peripheral]] (DMA1/DMA2) dedicated to transfers between internal peripherals and internal SRAM. These two DMA instances are coupled with a [[DMAMUX internal peripheral]] in charge of routing internal peripheral requests to DMA channels.
{{Info| Transfers between internal peripherals and DDR, via DMA1/DMA2, are possible but not recommended for high-bandwith or latency-critical transfers}}
The following figures show the different DMA configuration available on STM32MP1 and the associated request and data connections.
{{ReviewsComments|-- [[User:Gerald Baeza|Gerald Baeza]] ([[User talk:Gerald Baeza|talk]]) 14:53, 11 February 2020 (CET)<br />Figures to be inserted}}
For more information about the DMA controllers above and to know the DMA configuration that should be used with each internal peripheral, please refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]].

== ST Recommandations==
=== For Cortex-M4 execution context===
Cortex-M4 access by default internal SRAM for code and data.<br/>

In this context, DMA transfers will operate only between peripheral and internal SRAM.<br/>

That's why ST recommends to dedicate one [[DMA internal peripheral]] to Cortex-M4.<br/>


=== For Cortex-A7 secure execution context===
Cortex-A7 secure firmware is located in SYSRAM (both code and data). As the internal peripherals and the SYSRAM associated to the Cortex-A7 secure context are also secure, the MDMA must be used to support transfers between them because it is secure aware.

=== Cortex-A7 non-secure execution context===
Cortex-A7 non-secure firmware is mainly located in external memory (DDR). In consequence, DMA transfers will operate between peripherals and DDR.
But as the different internal peripherals don't have the same requirements in term of bandwidth, real time and flow control, customer will have to use one of the three DMA configuration described in [[#STM32MP15 DMA topology|STM32MP15 DMA topology]].
To ease the selection, the following table sums up possible choices for each peripheral and highlight the recommended configuration. Note that this configuration is set by default in [[STM32MP15 device tree]] (dtsi).
{{ReviewsComments|-- [[User:Gerald Baeza|Gerald Baeza]] ([[User talk:Gerald Baeza|talk]]) 14:51, 11 February 2020 (CET)<br />Table to be added}}

==ST reference boards default configuration==
<noinclude>
[[Category:STM32MP15 platform configuration|5]]</noinclude>

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Line 1: Line 1:
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__FORCETOC__
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== Article purpose ==
  +
The purpose of this article is to explain STM32MP15 DMA topology and the associated configurations recommended by ST.
  +
  +
== STM32MP15 DMA topology==
  +
STM32MP15 owns 3 DMA instances:
  +
* 1 [[MDMA internal peripheral]] dedicated to transfers between some internal peripherals and external memories (DDR) and between internal and external memories.
  +
* 2 [[DMA internal peripheral]] (DMA1/DMA2) dedicated to transfers between internal peripherals and internal SRAM. These two DMA instances are coupled with a [[DMAMUX internal peripheral]] in charge of routing internal peripheral requests to DMA channels.
  +
{{Info| Transfers between internal peripherals and DDR, via DMA1/DMA2, are possible but not recommended for high-bandwith or latency-critical transfers}}
  +
The following figures show the different DMA configuration available on STM32MP1 and the associated request and data connections.
  +
{{ReviewsComments|-- [[User:Gerald Baeza|Gerald Baeza]] ([[User talk:Gerald Baeza|talk]]) 14:53, 11 February 2020 (CET)<br />Figures to be inserted}}
  +
For more information about the DMA controllers above and to know the DMA configuration that should be used with each internal peripheral, please refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]].
  +
  +
== ST Recommandations==
  +
=== For Cortex-M4 execution context===
  +
Cortex-M4 access by default internal SRAM for code and data.<br/>
  +
In this context, DMA transfers will operate only between peripheral and internal SRAM.<br/>
  +
That's why ST recommends to dedicate one [[DMA internal peripheral]] to Cortex-M4.<br/>
  +
  +
=== For Cortex-A7 secure execution context===
  +
Cortex-A7 secure firmware is located in SYSRAM (both code and data). As the internal peripherals and the SYSRAM associated to the Cortex-A7 secure context are also secure, the MDMA must be used to support transfers between them because it is secure aware.
  +
  +
=== Cortex-A7 non-secure execution context===
  +
Cortex-A7 non-secure firmware is mainly located in external memory (DDR). In consequence, DMA transfers will operate between peripherals and DDR.
  +
But as the different internal peripherals don't have the same requirements in term of bandwidth, real time and flow control, customer will have to use one of the three DMA configuration described in [[#STM32MP15 DMA topology|STM32MP15 DMA topology]].
  +
To ease the selection, the following table sums up possible choices for each peripheral and highlight the recommended configuration. Note that this configuration is set by default in [[STM32MP15 device tree]] (dtsi).
  +
{{ReviewsComments|-- [[User:Gerald Baeza|Gerald Baeza]] ([[User talk:Gerald Baeza|talk]]) 14:51, 11 February 2020 (CET)<br />Table to be added}}
  +
  +
==ST reference boards default configuration==
  +
 
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{{ArticleApprovedVersion | Jean-ChristopheT | Nobody | No previous approved version | Automatic approval (article under construction) | 19Feb’19}}
  
 
[[Category:STM32MP15 platform configuration|5]]
  
[[Category:STM32MP15 platform configuration|5]]
 
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