Difference between revisions of "STM32MP13 OTP mapping"

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Applicable for STM32MP13x lines

Memory mapping[edit]

The table below gives an overview of the BSEC OTP memory mapping with useful information in the context of this Wiki reading.
OTP words 0 to 31 are called lower OTP and words 32 to 95 are called upper OTP.
Further information for the words and fields that are not explicitly described here can be found in the reference manual.

OTP word Bit field (size) Name Description
0 31-7 (25 bits) reserved
5, 3 (2 bits) is closed
  • b5,b3 = 0,0: device is in open state, authentication is optional.
  • b5,b3 = 1,1: device is in close state, authentication is mandatory.
Warning white.png Warning
These 'is_closed' bits must never be programmed to 1 on product without secure boot option available: this is indicated in the security field of the chip part number.
6, 4, 2-0 (5 bits) reserved
1-2 - - See the reference manual
3 31-30 (2 bits) HSE value
  • 0b00: HSE is autodetected.
  • 0b01: HSE is 24 MHz.
  • 0b10: HSE is 25 MHz.
  • 0b11: HSE is 26 MHz.
29-27 (3 bits) primary boot source
  • 0: No primary boot source is defined.
  • 1: FMC NAND
  • 2: QSPI NOR
  • 3: e•MMC™
  • 4: SD card
  • 5: QSPI NAND
26-24 (3 bits) secondary boot source
  • 0: No primary boot source is defined.
  • 1: FMC NAND
  • 2: QSPI NOR
  • 3: e•MMC™
  • 4: SD card
  • 5: QSPI NAND
23-16 (8 bits) boot source disable If it is different from zero, each bit disables a boot source.
  • 0b00000001: disable FMC NAND boot source
  • 0b00000010: disable QSPI NOR boot source
  • 0b00000100: disable e•MMC™ boot source
  • 0b00001000: disable SD boot source
  • 0b00010000: disable UART boot source
  • 0b00100000: disable USB boot source
  • 0b01000000: disable QSPI NAND boot source
15 (1 bit) data cache disabling
  • 0: data cache is used by the ROM code.
  • 1: data cache is not used by the ROM code.
14-7 (8 bits) UART instances disabling If different from zero then each bit disables an UART instance
  • 0b00000001: reserved
  • 0b00000010: reserved
  • 0b00000100: disable USART3
  • 0b00001000: disable UART4
  • 0b00010000: disable UART5
  • 0b00100000: disable UART6
  • 0b01000000: disable UART7
  • 0b10000000: disable USART8
  • 0b11111111: all UART instances are enabled.
6 (1 bit) USB DP pullup disabling
  • 0: USB DP pull-up is set.
  • 1: USB DP pull-up is not set.
5 (1 bit) PLL disabling
  • 0: PLLs for CPU and AXI are enable on cold boot.
  • 1: PLLs for CPU and AXI are not enable on cold boot.
4-3 (2 bits) SD card memory interface
  • 0: SDMMC1 with default AFMux
  • 1: SDMMC1 with non default AFmux defined in OTP
  • 2: SDMMC2 with AFmux defined in OTP
2-1 (2 bits) e•MMC™ memory interface
  • 0: SDMMC2 with default AFMux
  • 1: SDMMC1 with AFmux defined in OTP
  • 2: SDMMC2 with non default AFmux defined in OTP
0 (1 bit) QSPI non default AFmux
  • 0: QSPI uses default AFMux.
  • 1: QSPI uses AFmux defined in OTP.
4 31-0 (32 bits) monotonic counter This is an anti rollback monotonic counter : on counter. On closed devices, the ROM code checks that if it is less or equal to the one stored in the loaded image header.
  • 0b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 32.
  • 0b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 31.
  • 0b...
  • 0b00000000000000000000000000000001: monotonic counter value is 1.
  • 0b00000000000000000000000000000000: monotonic counter value is 0.
5 -7 31-28 (4 bits) AFmux configuration - port1[3:0] Bank id
  • 0: unused
  • 1: Bank A
  • 2: Bank B
  • 3: Bank C
  • 4: Bank D
  • 5: Bank E
  • 6: Bank F
  • 7: Bank G
  • 8: Bank H
  • 9: Bank I
  • 10: Bank J
  • 11: Bank K
  • 12: Bank Z
  • 13: not applicable
  • 14: not applicable
  • 0b1111: Invalid configuration
27-24 (4 bits) AFmux configuration - pin1[3:0] Pin id
23-20 (4 bits) AFmux configuration - afmux1[3:0] AFmux value
19-16 (4 bits) AFmux configuration - mode1[3:0] Pin mode
  • 0: AF; No Pull; Low Speed
  • 1: AF; No Pull; Medium Speed
  • 2: AF; No Pull; High Speed
  • 3: AF; Pull Up; Low Speed
  • 4: AF; Pull Up; Medium Speed
  • 5: AF; Pull Up; High Speed
  • 6: AF; Pull Down; Low Speed
  • 7: AF; Pull Down; Medium Speed
  • 8: AF; Pull Down; High Speed
  • 9: GPIO Output High
  • 10: GPIO Output Low
  • 11: GPIO Input
  • 12: GPIO open drain; No pull
  • 13: GPIO open drain; Pull Up
  • 14: GPIO open drain; Pull Down
  • 15: GPIO analog mode
15-12 (4 bits) AFmux configuration - port0[3:0] Bank id
  • 0: unused
  • 1: Bank A
  • 2: Bank B
  • 3: Bank C
  • 4: Bank D
  • 5: Bank E
  • 6: Bank F
  • 7: Bank G
  • 8: Bank H
  • 9: Bank I
  • 10: Bank J
  • 11: Bank K
  • 12: Bank Z
  • 13: not applicable
  • 14: not applicable
  • 0b1111: Invalid configuration
11-8 (4 bits) AFmux configuration - pin0[3:0] Pin id
7-4 (4 bits) AFmux configuration - afmux0[3:0] AFmux value
3-0 (4 bits) AFmux configuration - mode0[3:0] Pin mode
  • 0: AF; No Pull; Low Speed
  • 1: AF; No Pull; Medium Speed
  • 2: AF; No Pull; High Speed
  • 3: AF; Pull Up; Low Speed
  • 4: AF; Pull Up; Medium Speed
  • 5: AF; Pull Up; High Speed
  • 6: AF; Pull Down; Low Speed
  • 7: AF; Pull Down; Medium Speed
  • 8: AF; Pull Down; High Speed
  • 9: GPIO Output High
  • 10: GPIO Output Low
  • 11: GPIO Input
  • 12: GPIO open drain; No pull
  • 13: GPIO open drain; Pull Up
  • 14: GPIO open drain; Pull Down
  • 15: GPIO analog mode
6 31-28 (4 bits) AFmux configuration - port3[3:0] Bank id
  • 0: unused
  • 1: Bank A
  • 2: Bank B
  • 3: Bank C
  • 4: Bank D
  • 5: Bank E
  • 6: Bank F
  • 7: Bank G
  • 8: Bank H
  • 9: Bank I
  • 10: Bank J
  • 11: Bank K
  • 12: Bank Z
  • 13: not applicable
  • 14: not applicable
  • 0b1111: Invalid configuration
27-24 (4 bits) AFmux configuration - pin3[3:0] Pin id
23-20 (4 bits) AFmux configuration - afmux3[3:0] AFmux value
19-16 (4 bits) AFmux configuration - mode3[3:0] Pin mode
  • 0: AF; No Pull; Low Speed
  • 1: AF; No Pull; Medium Speed
  • 2: AF; No Pull; High Speed
  • 3: AF; Pull Up; Low Speed
  • 4: AF; Pull Up; Medium Speed
  • 5: AF; Pull Up; High Speed
  • 6: AF; Pull Down; Low Speed
  • 7: AF; Pull Down; Medium Speed
  • 8: AF; Pull Down; High Speed
  • 9: GPIO Output High
  • 10: GPIO Output Low
  • 11: GPIO Input
  • 12: GPIO open drain; No pull
  • 13: GPIO open drain; Pull Up
  • 14: GPIO open drain; Pull Down
  • 15: GPIO analog mode
15-12 (4 bits) AFmux configuration - port2[3:0] Bank id
  • 0: unused
  • 1: Bank A
  • 2: Bank B
  • 3: Bank C
  • 4: Bank D
  • 5: Bank E
  • 6: Bank F
  • 7: Bank G
  • 8: Bank H
  • 9: Bank I
  • 10: Bank J
  • 11: Bank K
  • 12: Bank Z
  • 13: not applicable
  • 14: not applicable
  • 0b1111: Invalid configuration
11-8 (4 bits) AFmux configuration - pin2[3:0] Pin id
7-4 (4 bits) AFmux configuration - afmux2[3:0] AFmux value
3-0 (4 bits) AFmux configuration - mode2[3:0] Pin mode
  • 0: AF; No Pull; Low Speed
  • 1: AF; No Pull; Medium Speed
  • 2: AF; No Pull; High Speed
  • 3: AF; Pull Up; Low Speed
  • 4: AF; Pull Up; Medium Speed
  • 5: AF; Pull Up; High Speed
  • 6: AF; Pull Down; Low Speed
  • 7: AF; Pull Down; Medium Speed
  • 8: AF; Pull Down; High Speed
  • 9: GPIO Output High
  • 10: GPIO Output Low
  • 11: GPIO Input
  • 12: GPIO open drain; No pull
  • 13: GPIO open drain; Pull Up
  • 14: GPIO open drain; Pull Down
  • 15: GPIO analog mode
7 31-28 (4 bits) AFmux configuration - port5[3:0] Bank id
  • 0: unused
  • 1: Bank A
  • 2: Bank B
  • 3: Bank C
  • 4: Bank D
  • 5: Bank E
  • 6: Bank F
  • 7: Bank G
  • 8: Bank H
  • 9: Bank I
  • 10: Bank J
  • 11: Bank K
  • 12: Bank Z
  • 13: not applicable
  • 14: not applicable
  • 0b1111: Invalid configuration
27-24 (4 bits) AFmux configuration - pin5[3:0] Pin id
23-20 (4 bits) AFmux configuration - afmux5[3:0] AFmux value
19-16 (4 bits) AFmux configuration - mode5[3:0] Pin mode
  • 0: AF; No Pull; Low Speed
  • 1: AF; No Pull; Medium Speed
  • 2: AF; No Pull; High Speed
  • 3: AF; Pull Up; Low Speed
  • 4: AF; Pull Up; Medium Speed
  • 5: AF; Pull Up; High Speed
  • 6: AF; Pull Down; Low Speed
  • 7: AF; Pull Down; Medium Speed
  • 8: AF; Pull Down; High Speed
  • 9: GPIO Output High
  • 10: GPIO Output Low
  • 11: GPIO Input
  • 12: GPIO open drain; No pull
  • 13: GPIO open drain; Pull Up
  • 14: GPIO open drain; Pull Down
  • 15: GPIO analog mode
15-12 (4 bits) AFmux configuration - port4[3:0] Bank id
  • 0: unused
  • 1: Bank A
  • 2: Bank B
  • 3: Bank C
  • 4: Bank D
  • 5: Bank E
  • 6: Bank F
  • 7: Bank G
  • 8: Bank H
  • 9: Bank I
  • 10: Bank J
  • 11: Bank K
  • 12: Bank Z
  • 13: not applicable
  • 14: not applicable
  • 0b1111: Invalid configuration
11-8 (4 bits) AFmux configuration - pin4[3:0] Pin id
7-4 (4 bits) AFmux configuration - afmux4[3:0] AFmux value
3-0 (4 bits) AFmux configuration - mode4[3:0] Pin mode
  • 0: AF; No Pull; Low Speed
  • 1: AF; No Pull; Medium Speed
  • 2: AF; No Pull; High Speed
  • 3: AF; Pull Up; Low Speed
  • 4: AF; Pull Up; Medium Speed
  • 5: AF; Pull Up; High Speed
  • 6: AF; Pull Down; Low Speed
  • 7: AF; Pull Down; Medium Speed
  • 8: AF; Pull Down; High Speed
  • 9: GPIO Output High
  • 10: GPIO Output Low
  • 11: GPIO Input
  • 12: GPIO open drain; No pull
  • 13: GPIO open drain; Pull Up
  • 14: GPIO open drain; Pull Down
  • 15: GPIO analog mode
8 31-0 (32 bits) reserved
9 31 (1 bit) nand param stored in otp FMC NAND parameters storage flag
  • 0b0: NAND parameters are not stored here in OTP and are available via an ‘ONFI’ compliant get parameter command.
  • 0b1: NAND parameters are stored here in OTP.

Notes:

  • serial NAND parameters must always be stored in OTP. This bit is useless for serial NAND.
  • there are two NAND parameters banks. The value of NAND configuration distribution determines the bank to be used.
30-29 (2 bits) nand page size[1:0] FMC or serial NAND page size
  • 0: page size is 2 Kbytes.
  • 1: page size is 4 Kbytes.
  • 2: page size is 8 Kbytes.
  • 3: reserved

Note: this parameter is part of NAND parameters bank1.

28-27 (2 bits) nand block size[1:0] FMC or serial NAND block size
  • 0: block size is 64 pages.
  • 1: block size is 128 pages.
  • 2: block size is 256 pages.
  • 3: reserved

Note: this parameter is part of NAND parameters bank1.

26-19 (8 bits) nand block nb[7:0] FMC or serial NAND number of blocks in unit of 256 blocks (nb blocks = N * 256)
18 (1 bit) fmc nand width FMC NAND width
  • 0: FMC NAND is 8 bits.
  • 1: FMC NAND is 16 bits.

Note: this parameter is part of NAND parameters bank1.

17-15 (3 bits) fmc ecc bit nb[2:0] FMC NAND number of ECC bits
  • 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’.
  • 1: 1 bit ECC per 512 bytes, Hamming code
  • 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
  • 3: 8 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
  • 4: on-die ECC

Note: this parameter is part of NAND parameters bank1.

14 (1 bit) spinand needs plane select Serial NAND needs plane select.
  • 0: serial NAND plane select is not needed.
  • 1: serial NAND plane select is needed.

Note: this parameter is part of NAND parameters bank1.

13-8 (6 bits) reserved
7 (1 bit) FSBL decryption priority
  • 0: use CRYP to priorise prioritize speed.
  • 1: use SAES to priorise prioritize security.
6 (1 bit) SSP success
  • 0: SSP is either not started or not finished.
  • 1: SSP is finished.
5 (1 bit) SSP request
  • 0: SSP has never been requested.
  • 1: SSP has been requested.
4 (1 bit) eMMC 128KB boot partition support
  • 0: BootROM does not support eMMC with 128KBytes boot partition.
  • 1: BootROM supports eMMC with 128KBytes boot partition.
3 (1 bit) disable ddr power optim Disable DDR PLL switch off sequence
  • 0: DDR DLL switch off sequence is enabled.
  • 1: DDR DLL switch off sequence is disabled.
2 (1 bit) disable HSE bypass detection
  • 0: HSE bypass detection is enabled.
  • 1: HSE bypass detection is disabled.
1 (1 bit) disable HSE frequency autodetection
  • 0: HSE frequency autodetection is enabled.
  • 1: HSE frequency autodetection is disabled.
0 (1 bit) disable ROM code traces
  • 0: ROM code traces is enabled.
  • 1: ROM code traces is disabled.
10 31-18 21 (14 11 bits) reserved
20-18 (3 bits) rng hctr value RNG HCTR value
  • 0:default RNG value, RNG_HTCR not modified.
  • 1: 0xA2B3 (unsigned long)
  • 2: 0xAA74 (unsigned long)
  • 3: 0xA6BA (unsigned long)
  • 4: 0x9AAE (unsigned long)
  • 5: 0x72AC (unsigned long)
  • 6: 0xAAC7 (unsigned long)
  • Other values: default RNG value, RNG_HTCR not modified.
17-16 (2 bits) nand page size[1:0] NAND parameters bank2 : FMC or serial NAND page size
  • 0: page size is 2 Kbytes.
  • 1: page size is 4 Kbytes.
  • 2: page size is 8 Kbytes.
  • 3: reserved
15-14 (2 bits) nand block size[1:0] NAND parameters bank2 : FMC or serial NAND block size
  • 0: block size is 64 pages.
  • 1: block size is 128 pages.
  • 2: block size is 256 pages.
  • 3: reserved
13-6 (8 bits) nand block nb[7:0] NAND parameters bank2 : FMC or serial NAND number of blocks in unit of 256 blocks (nb blocks = N * 256)
5 (1 bit) fmc nand width NAND parameters bank2 : FMC NAND width
  • 0: FMC NAND is 8 bits.
  • 1: FMC NAND is 16 bits.
4-2 (3 bits) fmc ecc bit nb[2:0] NAND parameters bank2 : FMC NAND number of ECC bits
  • 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’.
  • 1: 1 bit ECC per 512 bytes, Hamming code
  • 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
  • 3: 8 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
  • 4: on-die ECC
1 (1 bit) spinand needs plane select NAND parameters bank2 : serial NAND needs plane select.
  • 0: serial NAND plane select is not needed.
  • 1: serial NAND plane select is needed.
0 (1 bit) NAND configuration distribution Distribution of NAND parameters bank1 and bank2.
  • 0: FMC NAND configuration in bank2 / serial NAND configuration in bank1
  • 1: FMC NAND configuration in bank1 / serial NAND configuration in bank2
11-21 - - See the reference manual.
22 31-8 (24 bits) reserved
7-0 (8 bits) signing key id monotonic counter This is an a key revocation monotonic counter used by the ROM to checks that check if it is less or equal to the active signing key id stored in the loaded image header.
  • 0b1xxxxxxx: monotonic counter value is 8
  • 0b01xxxxxx: monotonic counter value is 7
  • 0b...
  • 0b00000001: monotonic counter value is 1
  • 0b00000000: monotonic counter value is 0
23 - - See the reference manual.
24 31-0 (32 bits) PKHTH[31:0] PKHTH1 The Public Key Hashes Table Hash (PKHTH) is the SHA256 hash of the 8 SHA256 hashes of the 8 ECDSA public keys usable for the Secure secure boot.

If hash = 01 02 03 04 05 06 07 08… then PKHTH1 = 0x01020304, PKHTH2 = 0x05060708, etc,…

25 31-0 (32 bits) PKHTH[63:32] PKHTH2
26 31-0 (32 bits) PKHTH[95:64] PKHTH3
27 31-0 (32 bits) PKHTH[128:96] PKHTH4
28 31-0 (32 bits) PKHTH[159:128] PKHTH5
29 31-0 (32 bits) PKHTH[191:160] PKHTH6
30 31-0 (32 bits) PKHTH[223:192] PKHTH7
31 31-0 (32 bits) PKHTH[255:224] PKHTH8
32-55 - - See the reference manual.
56 31-0 (32 bits) rma unlock passwd Password A password is required for RMA unlock request.
57 31-0 mac1[47:16] ETH MAC addresses for STMicroelectronics boards
58 15-0 mac1[15:0]
31-16 mac2[47:32]
59 31-0 mac2[31:0]
60-91 - - See the reference manual.
92 31-0 (32 bits) EDMK[31:0] The Encryption Decryption Master Key (EDMK) is used in combination with the derivation constant stored in the header file to derive the FSBL decryption key.
93 31-0 (32 bits) EDMK[63:32]
94 31-0 (32 bits) EDMK[95:64]
95 31-0 (32 bits) EDMK[128:96]


<noinclude>{{ApplicableFor
|MPUs list= STM32MP13x
|MPUs checklist= STM32MP13x, STM32MP15x
}}</noinclude>


==Memory mapping==
The table below gives an overview of the [[BSEC internal peripheral|BSEC]] OTP memory mapping with useful information in the context of this Wiki reading. <br>

OTP words 0 to 31 are called lower OTP and words 32 to 95 are called upper OTP.<br>

Further information for the words and fields that are not explicitly described here can be found in the [[STM32MP13 resources#Reference manuals|reference 
manual]].<br>


{| class="st-table" style="width: 100%;"
|- style="background: {{STLightGrey}};"
! style="width: 8%;" | OTP word
! style="width: 17%;" | Bit field (size)
! style="width: 20%;" | Name
! style="width: 50%;" | Description
|-
| rowspan=3 | 0
| 31-7 (25 bits) 
| reserved
| 
|-
| 5, 3 (2 bits)
| <span id="is closed">is closed</span>

| <div class="mw-collapsible mw-collapsed">

* b5,b3 = 0,0: device is in open state, authentication is optional.
* b5,b3 = 1,1: device is in close state, authentication is mandatory.</div>


{{Warning| These 'is_closed' bits must never be programmed to 1 on product without secure boot option available: this is indicated in the ''security'' field of the chip [[STM32MP13_microprocessor#Part_number_codification|part number]].}}
|-
| 6, 4, 2-0 (5 bits)
| reserved
|
|-
| 1-2
| -
| -
| See the [[STM32MP13 resources#Reference manuals|reference manual]]
|-
| rowspan=11 | 3
| 31-30 (2 bits)
| <span id="HSE value">HSE value</span>

|<div class="mw-collapsible mw-collapsed">

* 0b00: HSE is autodetected.

* 0b01: HSE is 24 MHz.

* 0b10: HSE is 25 MHz.

* 0b11: HSE is 26 MHz.
</div>

|-
| 29-27 (3 bits)
| <span id="primary boot source">primary boot source</span>

| <div class="mw-collapsible mw-collapsed">

* 0: No primary boot source is defined.

* 1: FMC NAND
* 2: QSPI NOR
* 3: ''e''•MMC™
* 4: SD card
* 5: QSPI NAND</div>

|-
| 26-24 (3 bits)
| <span id="secondary boot source">secondary boot source</span>

| <div class="mw-collapsible mw-collapsed">

* 0: No primary boot source is defined.

* 1: FMC NAND
* 2: QSPI NOR
* 3: ''e''•MMC™
* 4: SD card
* 5: QSPI NAND</div>

|-
| 23-16 (8 bits)
| <span id="boot source disable">boot source disable</span>

| If it is different from zero, each bit disables a boot source.
<div class="mw-collapsible mw-collapsed">

* 0b00000001: disable FMC NAND boot source
* 0b00000010: disable QSPI NOR boot source
* 0b00000100: disable ''e''•MMC™ boot source
* 0b00001000: disable SD boot source
* 0b00010000: disable UART boot source
* 0b00100000: disable USB boot source
* 0b01000000: disable QSPI NAND boot source</div>

|-
| 15 (1 bit)
| <span id="data cache disabling">data cache disabling</span>

| <div class="mw-collapsible mw-collapsed">

* 0: data cache is used by the ROM code.

* 1: data cache is not used by the ROM code.
</div>

|-
| 14-7 (8 bits)
| <span id="UART instances disabling">UART instances disabling</span>

| If different from zero then each bit disables an UART instance<div class="mw-collapsible mw-collapsed">

* 0b00000001: reserved
* 0b00000010: reserved
* 0b00000100: disable USART3
* 0b00001000: disable UART4
* 0b00010000: disable UART5
* 0b00100000: disable UART6
* 0b01000000: disable UART7
* 0b10000000: disable USART8
* 0b11111111: all UART instances are enabled.
</div>

|-
| 6 (1 bit)
| <span id="USB DP pullup disabling">USB DP pullup disabling</span>

| <div class="mw-collapsible mw-collapsed">

* 0: USB DP pull-up is set.

* 1: USB DP pull-up is not set.
</div>

|-
| 5 (1 bit)
| <span id="PLL disabling">PLL disabling</span>

| <div class="mw-collapsible mw-collapsed">

* 0: PLLs for CPU and AXI are enable on cold boot.

* 1: PLLs for CPU and AXI are not enable on cold boot.
</div>

|-
| 4-3 (2 bits)
| <span id="SD card memory interface">SD card memory interface</span>

| <div class="mw-collapsible mw-collapsed">

* 0: SDMMC1 with default AFMux
* 1: SDMMC1 with non default AFmux defined in OTP
* 2: SDMMC2 with AFmux defined in OTP</div>

|-
| 2-1 (2 bits)
| <span id="''e''•MMC™ memory interface">''e''•MMC™ memory interface</span>

| <div class="mw-collapsible mw-collapsed">

* 0: SDMMC2 with default AFMux
* 1: SDMMC1 with AFmux defined in OTP
* 2: SDMMC2 with non default AFmux defined in OTP</div>

|-
| 0 (1 bit)
| <span id="QSPI non default AFmux">QSPI non default AFmux</span>

| <div class="mw-collapsible mw-collapsed">

* 0: QSPI uses default AFMux.

* 1: QSPI uses AFmux defined in OTP.
</div>

|-
| 4
| 31-0 (32 bits)
| <span id="version monotonic counter">monotonic counter</span>

| This is an anti rollback monotonic counter : on . On closed devices, the ROM code checks thatif it is less or equal to the one stored in the loaded image header.<div class="mw-collapsible mw-collapsed">

* 0b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 32.

* 0b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 31.

* 0b...
* 0b00000000000000000000000000000001: monotonic counter value is 1.

* 0b00000000000000000000000000000000: monotonic counter value is 0.
</div>

|-
| rowspan=8 | 5-7

| 31-28 (4 bits)
| <span id="AFmux configuration">AFmux configuration</span> - port1[3:0]
| Bank id<div class="mw-collapsible mw-collapsed">

* 0: unused
* 1: Bank A
* 2: Bank B
* 3: Bank C
* 4: Bank D
* 5: Bank E
* 6: Bank F
* 7: Bank G
* 8: Bank H
* 9: Bank I
* 10: Bank J
* 11: Bank K
* 12: Bank Z
* 13: not applicable
* 14: not applicable
* 0b1111: Invalid configuration</div>

|-
| 27-24 (4 bits)
| AFmux configuration - pin1[3:0]
| Pin id
|-
| 23-20 (4 bits)
| AFmux configuration - afmux1[3:0]
| AFmux value
|-
| 19-16 (4 bits)
| AFmux configuration - mode1[3:0]
| Pin mode<div class="mw-collapsible mw-collapsed">

* 0: AF; No Pull; Low Speed
* 1: AF; No Pull; Medium Speed
* 2: AF; No Pull; High Speed
* 3: AF; Pull Up; Low Speed
* 4: AF; Pull Up; Medium Speed
* 5: AF; Pull Up;  High Speed
* 6: AF; Pull Down; Low Speed
* 7: AF; Pull Down; Medium Speed
* 8: AF; Pull Down; High Speed
* 9: GPIO Output High
* 10: GPIO Output Low
* 11: GPIO Input
* 12: GPIO open drain; No pull
* 13: GPIO open drain; Pull Up
* 14: GPIO open drain; Pull Down
* 15: GPIO analog mode</div>

|-
| 15-12 (4 bits)
| AFmux configuration - port0[3:0]
| Bank id<div class="mw-collapsible mw-collapsed">

* 0: unused
* 1: Bank A
* 2: Bank B
* 3: Bank C
* 4: Bank D
* 5: Bank E
* 6: Bank F
* 7: Bank G
* 8: Bank H
* 9: Bank I
* 10: Bank J
* 11: Bank K
* 12: Bank Z
* 13: not applicable
* 14: not applicable
* 0b1111: Invalid configuration</div>

|-
| 11-8 (4 bits)
| AFmux configuration - pin0[3:0]
| Pin id
|-
| 7-4 (4 bits)
| AFmux configuration - afmux0[3:0]
| AFmux value
|-
| 3-0 (4 bits)
| AFmux configuration - mode0[3:0]
| Pin mode<div class="mw-collapsible mw-collapsed">

* 0: AF; No Pull; Low Speed
* 1: AF; No Pull; Medium Speed
* 2: AF; No Pull; High Speed
* 3: AF; Pull Up; Low Speed
* 4: AF; Pull Up; Medium Speed
* 5: AF; Pull Up;  High Speed
* 6: AF; Pull Down; Low Speed
* 7: AF; Pull Down; Medium Speed
* 8: AF; Pull Down; High Speed
* 9: GPIO Output High
* 10: GPIO Output Low
* 11: GPIO Input
* 12: GPIO open drain; No pull
* 13: GPIO open drain; Pull Up
* 14: GPIO open drain; Pull Down
* 15: GPIO analog mode</div>

|-
| rowspan=1 | 8
| 31-0 (8 | 6
| 31-28 (4 bits)
| <span id="AFmux configuration">AFmux configuration</span> - port3[3:0]
| Bank id<div class="mw-collapsible mw-collapsed">

* 0: unused
* 1: Bank A
* 2: Bank B
* 3: Bank C
* 4: Bank D
* 5: Bank E
* 6: Bank F
* 7: Bank G
* 8: Bank H
* 9: Bank I
* 10: Bank J
* 11: Bank K
* 12: Bank Z
* 13: not applicable
* 14: not applicable
* 0b1111: Invalid configuration</div>

|-
| 27-24 (4 bits)
| AFmux configuration - pin3[3:0]
| Pin id
|-
| 23-20 (4 bits)
| AFmux configuration - afmux3[3:0]
| AFmux value
|-
| 19-16 (4 bits)
| AFmux configuration - mode3[3:0]
| Pin mode<div class="mw-collapsible mw-collapsed">

* 0: AF; No Pull; Low Speed
* 1: AF; No Pull; Medium Speed
* 2: AF; No Pull; High Speed
* 3: AF; Pull Up; Low Speed
* 4: AF; Pull Up; Medium Speed
* 5: AF; Pull Up;  High Speed
* 6: AF; Pull Down; Low Speed
* 7: AF; Pull Down; Medium Speed
* 8: AF; Pull Down; High Speed
* 9: GPIO Output High
* 10: GPIO Output Low
* 11: GPIO Input
* 12: GPIO open drain; No pull
* 13: GPIO open drain; Pull Up
* 14: GPIO open drain; Pull Down
* 15: GPIO analog mode</div>

|-
| 15-12 (4 bits)
| AFmux configuration - port2[3:0]
| Bank id<div class="mw-collapsible mw-collapsed">

* 0: unused
* 1: Bank A
* 2: Bank B
* 3: Bank C
* 4: Bank D
* 5: Bank E
* 6: Bank F
* 7: Bank G
* 8: Bank H
* 9: Bank I
* 10: Bank J
* 11: Bank K
* 12: Bank Z
* 13: not applicable
* 14: not applicable
* 0b1111: Invalid configuration</div>

|-
| 11-8 (4 bits)
| AFmux configuration - pin2[3:0]
| Pin id
|-
| 7-4 (4 bits)
| AFmux configuration - afmux2[3:0]
| AFmux value
|-
| 3-0 (4 bits)
| AFmux configuration - mode2[3:0]
| Pin mode<div class="mw-collapsible mw-collapsed">

* 0: AF; No Pull; Low Speed
* 1: AF; No Pull; Medium Speed
* 2: AF; No Pull; High Speed
* 3: AF; Pull Up; Low Speed
* 4: AF; Pull Up; Medium Speed
* 5: AF; Pull Up;  High Speed
* 6: AF; Pull Down; Low Speed
* 7: AF; Pull Down; Medium Speed
* 8: AF; Pull Down; High Speed
* 9: GPIO Output High
* 10: GPIO Output Low
* 11: GPIO Input
* 12: GPIO open drain; No pull
* 13: GPIO open drain; Pull Up
* 14: GPIO open drain; Pull Down
* 15: GPIO analog mode</div>

|-
| rowspan=8 | 7
| 31-28 (4 bits)
| <span id="AFmux configuration">AFmux configuration</span> - port5[3:0]
| Bank id<div class="mw-collapsible mw-collapsed">

* 0: unused
* 1: Bank A
* 2: Bank B
* 3: Bank C
* 4: Bank D
* 5: Bank E
* 6: Bank F
* 7: Bank G
* 8: Bank H
* 9: Bank I
* 10: Bank J
* 11: Bank K
* 12: Bank Z
* 13: not applicable
* 14: not applicable
* 0b1111: Invalid configuration</div>

|-
| 27-24 (4 bits)
| AFmux configuration - pin5[3:0]
| Pin id
|-
| 23-20 (4 bits)
| AFmux configuration - afmux5[3:0]
| AFmux value
|-
| 19-16 (4 bits)
| AFmux configuration - mode5[3:0]
| Pin mode<div class="mw-collapsible mw-collapsed">

* 0: AF; No Pull; Low Speed
* 1: AF; No Pull; Medium Speed
* 2: AF; No Pull; High Speed
* 3: AF; Pull Up; Low Speed
* 4: AF; Pull Up; Medium Speed
* 5: AF; Pull Up;  High Speed
* 6: AF; Pull Down; Low Speed
* 7: AF; Pull Down; Medium Speed
* 8: AF; Pull Down; High Speed
* 9: GPIO Output High
* 10: GPIO Output Low
* 11: GPIO Input
* 12: GPIO open drain; No pull
* 13: GPIO open drain; Pull Up
* 14: GPIO open drain; Pull Down
* 15: GPIO analog mode</div>

|-
| 15-12 (4 bits)
| AFmux configuration - port4[3:0]
| Bank id<div class="mw-collapsible mw-collapsed">

* 0: unused
* 1: Bank A
* 2: Bank B
* 3: Bank C
* 4: Bank D
* 5: Bank E
* 6: Bank F
* 7: Bank G
* 8: Bank H
* 9: Bank I
* 10: Bank J
* 11: Bank K
* 12: Bank Z
* 13: not applicable
* 14: not applicable
* 0b1111: Invalid configuration</div>

|-
| 11-8 (4 bits)
| AFmux configuration - pin4[3:0]
| Pin id
|-
| 7-4 (4 bits)
| AFmux configuration - afmux4[3:0]
| AFmux value
|-
| 3-0 (4 bits)
| AFmux configuration - mode4[3:0]
| Pin mode<div class="mw-collapsible mw-collapsed">

* 0: AF; No Pull; Low Speed
* 1: AF; No Pull; Medium Speed
* 2: AF; No Pull; High Speed
* 3: AF; Pull Up; Low Speed
* 4: AF; Pull Up; Medium Speed
* 5: AF; Pull Up;  High Speed
* 6: AF; Pull Down; Low Speed
* 7: AF; Pull Down; Medium Speed
* 8: AF; Pull Down; High Speed
* 9: GPIO Output High
* 10: GPIO Output Low
* 11: GPIO Input
* 12: GPIO open drain; No pull
* 13: GPIO open drain; Pull Up
* 14: GPIO open drain; Pull Down
* 15: GPIO analog mode</div>

|-
| rowspan=1 | 8
| 31-0 (32 bits)
| reserved
|
|-
| rowspan=16| 9
| 31 (1 bit)
| <span id="nand param stored in otp">nand param stored in otp</span>

| FMC NAND parameters storage flag<div class="mw-collapsible mw-collapsed">

* 0b0: NAND parameters are not stored here in OTP and are available via an ‘ONFI’ compliant get parameter command.

* 0b1: NAND parameters are stored here in OTP.
</div>
<small>Notes:<br>

* serial NAND parameters must always be stored in OTP.  This bit is useless for serial NAND.
* there are two NAND parameters banks. The value of [[STM32MP13 OTP mapping#NAND configuration distribution|NAND configuration distribution]] determines the bank to be used.
|-
| 30-29 (2 bits)
| <span id="nand page size">nand page size[1:0]</span>

| FMC or serial NAND page size<div class="mw-collapsible mw-collapsed">

* 0: page size is 2 Kbytes.

* 1: page size is 4 Kbytes.

* 2: page size is 8 Kbytes.

* 3: reserved</div>
<small>Note: this parameter is part of NAND parameters bank1.</small>

|-
| 28-27 (2 bits)
| <span id="nand block size">nand block size[1:0]</span>

| FMC or serial NAND block size<div class="mw-collapsible mw-collapsed">

* 0: block size is 64 pages.

* 1: block size is 128 pages.

* 2: block size is 256 pages.

* 3: reserved</div>
<small>Note: this parameter is part of NAND parameters bank1.</small>

|-
| 26-19 (8 bits)
| <span id="nand block nb">nand block nb[7:0]</span>

| FMC or serial NAND number of blocks in unit of 256 blocks (nb blocks = N * 256)
|-
| 18 (1 bit)
| <span id="fmc nand width">fmc nand width</span>

| FMC NAND width<div class="mw-collapsible mw-collapsed">

* 0: FMC NAND is 8 bits.

* 1: FMC NAND is 16 bits.
</div>
<small>Note: this parameter is part of NAND parameters bank1.</small>

|-
| 17-15 (3 bits)
| <span id="fmc ecc bit nb">fmc ecc bit nb[2:0]</span>

| FMC NAND number of ECC bits<div class="mw-collapsible mw-collapsed">

* 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’.

* 1: 1 bit ECC per 512 bytes, Hamming code
* 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
* 3: 8 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
* 4: on-die ECC</div>
<small>Note: this parameter is part of NAND parameters bank1.</small>

|-
| 14 (1 bit)
| <span id="spinand needs plane select">spinand needs plane select</span>

| Serial NAND needs plane select.
<div class="mw-collapsible mw-collapsed">

* 0: serial NAND plane select is not needed.

* 1: serial NAND plane select is needed.
</div>
<small>Note: this parameter is part of NAND parameters bank1.</small>

|-
| 13-8 (6 bits)
| reserved
| 
|-
| rowspan = 1 | 7 (1 bit)
|  <span id="FSBL decryption priority">FSBL decryption priority</span>

| <div class="mw-collapsible mw-collapsed">

* 0: use CRYP to prioriseprioritize speed.

* 1: use SAES to prioriseprioritize security.
</div>

|-
| rowspan = 1 | 6 (1 bit)
|  <span id="SSP success mp13">SSP success</span>

| <div class="mw-collapsible mw-collapsed">

* 0: SSP is either not started or not finished.

* 1: SSP is finished.
</div>

|-
| rowspan = 1 | 5 (1 bit)
| <span id="SSP request mp13">SSP request</span>

| <div class="mw-collapsible mw-collapsed">

* 0: SSP has never been requested.

* 1: SSP has been requested.
</div>

|-
| rowspan = 1 | 4 (1 bit)
|  <span id="eMMC 128KB boot partition support">eMMC 128KB boot partition support</span><br>

| <div class="mw-collapsible mw-collapsed">

* 0: BootROM does not support eMMC with 128KBytes boot partition.

* 1: BootROM supports eMMC with 128KBytes boot partition.
</div>

|-
| 3 (1 bit)
| <span id="disable ddr power optim">disable ddr power optim</span>

| Disable DDR PLL switch off sequence<div class="mw-collapsible mw-collapsed">

* 0: DDR DLL switch off sequence is enabled. 

* 1: DDR DLL switch off sequence is disabled.
</div>

|-
| 2 (1 bit)
| <span id="disable HSE bypass detection">disable HSE bypass detection</span>

| <div class="mw-collapsible mw-collapsed">

* 0: HSE bypass detection is enabled.

* 1: HSE bypass detection is disabled.
</div>

|-
| 1 (1 bit)
| <span id="disable HSE frequency autodetection">disable HSE frequency autodetection</span>

| <div class="mw-collapsible mw-collapsed">

* 0: HSE frequency autodetection is enabled.

* 1: HSE frequency autodetection is disabled.
</div>

|-
| 0 (1 bit)
| <span id="disable ROM code traces">disable ROM code traces</span>

| <div class="mw-collapsible mw-collapsed">

* 0: ROM code traces is enabled.

* 1: ROM code traces is disabled.
</div>

|-
| rowspan=89 | 10
| 31-18 (1421 (11 bits)
| reserved
|
|-
| 20-18 (3 bits)
| <span id="rng hctr value">rng hctr value</span>

| RNG HCTR value<div class="mw-collapsible mw-collapsed">

* 0:default RNG value, RNG_HTCR not modified.
* 1: 0xA2B3 (unsigned long)
* 2: 0xAA74 (unsigned long)
* 3: 0xA6BA (unsigned long)
* 4: 0x9AAE (unsigned long)
* 5: 0x72AC (unsigned long)
* 6: 0xAAC7 (unsigned long)
*Other values: default RNG value, RNG_HTCR not modified.</div>

|-
| 17-16 (2 bits)
| <span id="nand page size bank2">nand page size[1:0]</span>

| NAND parameters bank2 : FMC or serial NAND page size<div class="mw-collapsible mw-collapsed">

* 0: page size is 2 Kbytes.

* 1: page size is 4 Kbytes.

* 2: page size is 8 Kbytes.

* 3: reserved</div>

|-
| 15-14 (2 bits)
| <span id="nand block size bank2">nand block size[1:0]</span>

| NAND parameters bank2 : FMC or serial NAND block size<div class="mw-collapsible mw-collapsed">

* 0: block size is 64 pages.

* 1: block size is 128 pages.

* 2: block size is 256 pages.

* 3: reserved</div>

|-
| 13-6 (8 bits)
| <span id="nand block nb bank2">nand block nb[7:0]</span>

| NAND parameters bank2 : FMC or serial NAND number of blocks in unit of 256 blocks (nb blocks = N * 256)
|-
| 5 (1 bit)
| <span id="fmc nand width bank2">fmc nand width</span>

| NAND parameters bank2 : FMC NAND width<div class="mw-collapsible mw-collapsed">

* 0: FMC NAND is 8 bits.

* 1: FMC NAND is 16 bits.
</div>

|-
| 4-2 (3 bits)
| <span id="fmc ecc bit nb bank2">fmc ecc bit nb[2:0]</span>

| NAND parameters bank2 : FMC NAND number of ECC bits<div class="mw-collapsible mw-collapsed">

* 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’.

* 1: 1 bit ECC per 512 bytes, Hamming code
* 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
* 3: 8 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
* 4: on-die ECC</div>

|-
| 1 (1 bit)
| <span id="spinand needs plane select bank2">spinand needs plane select</span>

| NAND parameters bank2 : serial NAND needs plane select.
<div class="mw-collapsible mw-collapsed">

* 0: serial NAND plane select is not needed.

* 1: serial NAND plane select is needed.
</div>

|-
| 0 (1 bit)
| <span id="NAND configuration distribution">NAND configuration distribution</span>

| Distribution of NAND parameters bank1 and bank2.<div class="mw-collapsible mw-collapsed">

* 0: FMC NAND configuration in bank2 / serial NAND configuration in bank1
* 1: FMC NAND configuration in bank1 / serial NAND configuration in bank2</div>

|-
| 11-21
| -
| -
| See the [[STM32MP13 resources#Reference manuals|reference manual]].

|-
| rowspan=2 | 22
| 31-8 (24 bits)
| reserved
|
|-
| 7-0 (8 bits)
| <span id="signing key id monotonic counter">signing key id monotonic counter</span>

| This is ana key revocation monotonic counter used by the ROM to checks thatcheck if it is less or equal to the active signing key id stored in the loaded image header.<div class="mw-collapsible mw-collapsed">

* 0b1xxxxxxx: monotonic counter value is 8
* 0b01xxxxxx: monotonic counter value is 7
* 0b...
* 0b00000001: monotonic counter value is 1
* 0b00000000: monotonic counter value is 0</div>

|-
| 23
| -
| -
| See the [[STM32MP13 resources#Reference manuals|reference manual]].

|-
| 24
| 31-0 (32 bits)
| <span id="PKHTH">PKHTH[31:0]PKHTH1</span>

| rowspan=8 | The Public Key Hashes Table Hash (PKHTH) is the SHA256 hash of the 8 SHA256 hashes of the 8 ECDSA public keys usable for the Securesecure boot
.<br>


If hash = 01 02 03 04 05 06 07 08… then PKHTH1 = 0x01020304, PKHTH2 = 0x05060708, etc,… |-
| 25
| 31-0 (32 bits)
| PKHTH[63:32]PKHTH2

|-
| 26
| 31-0 (32 bits)
| PKHTH[95:64]PKHTH3

|-
| 27
| 31-0 (32 bits)
| PKHTH[128:96]PKHTH4

|-
| 28
| 31-0 (32 bits)
| PKHTH[159:128]PKHTH5

|-
| 29
| 31-0 (32 bits)
| PKHTH[191:160]PKHTH6

|-
| 30
| 31-0 (32 bits)
| PKHTH[223:192]PKHTH7

|-
| 31
| 31-0 (32 bits)
| PKHTH[255:224]PKHTH8

|-
| 32-55
| -
| -
| See the [[STM32MP13 resources#Reference manuals|reference manual]].

|-
| 56
| 31-0 (32 bits)
| <span id="rma unlock passwd">rma unlock passwd</span>

| Password A password is required for RMA unlock request.

|-
| 57
| 31-0
| <span id="MAC address">mac1[47:16]</span>

| rowspan=4 | [[ETH internal peripheral|ETH]] MAC addresses for STMicroelectronics boards
|-
| rowspan=2 | 58
| 15-0
| mac1[15:0]
|-
| 31-16
| mac2[47:32]
|-
| 59
| 31-0
| mac2[31:0]
|-
| 60-91
| -
| -
| See the [[STM32MP13 resources#Reference manuals|reference manual]].

|-
| 92
| 31-0 (32 bits)
| <span id="EDMK">EDMK[31:0]</span>

| rowspan=4 | The Encryption Decryption Master Key (EDMK) is used in combination with the derivation constant stored in the header file to derive the FSBL decryption key.
|-
| 93
| 31-0 (32 bits)
| EDMK[63:32]
|-
| 94
| 31-0 (32 bits)
| EDMK[95:64]
|-
| 95
| 31-0 (32 bits)
| EDMK[128:96]
|-
|}<noinclude>

[[Category:STM32MP13 platform configuration|1]]{{PublicationRequestId | 24644 | 2022-09-26 |}}</noinclude>
(10 intermediate revisions by 4 users not shown)
Line 45: Line 45:
 
|
 
|
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0b00: HSE is autodetected
+
* 0b00: HSE is autodetected.
* 0b01: HSE is 24 MHz
+
* 0b01: HSE is 24 MHz.
* 0b10: HSE is 25 MHz
+
* 0b10: HSE is 25 MHz.
* 0b11: HSE is 26 MHz
+
* 0b11: HSE is 26 MHz.
 
</div>
 
</div>
 
|-
 
|-
Line 54: Line 54:
 
| <span id="primary boot source">primary boot source</span>
 
| <span id="primary boot source">primary boot source</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: No primary boot source is defined
+
* 0: No primary boot source is defined.
 
* 1: FMC NAND
 
* 1: FMC NAND
 
* 2: QSPI NOR
 
* 2: QSPI NOR
Line 65: Line 65:
 
| <span id="secondary boot source">secondary boot source</span>
 
| <span id="secondary boot source">secondary boot source</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: No primary boot source is defined
+
* 0: No primary boot source is defined.
 
* 1: FMC NAND
 
* 1: FMC NAND
 
* 2: QSPI NOR
 
* 2: QSPI NOR
Line 75: Line 75:
 
| 23-16 (8 bits)
 
| 23-16 (8 bits)
 
| <span id="boot source disable">boot source disable</span>
 
| <span id="boot source disable">boot source disable</span>
| If different from zero each bit disables a boot source
+
| If it is different from zero, each bit disables a boot source.
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
 
* 0b00000001: disable FMC NAND boot source
 
* 0b00000001: disable FMC NAND boot source
Line 89: Line 89:
 
| <span id="data cache disabling">data cache disabling</span>
 
| <span id="data cache disabling">data cache disabling</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: data cache is used by the ROM code
+
* 0: data cache is used by the ROM code.
* 1: data cache is not used by the ROM code
+
* 1: data cache is not used by the ROM code.
 
</div>
 
</div>
 
|-
 
|-
Line 105: Line 105:
 
* 0b01000000: disable UART7
 
* 0b01000000: disable UART7
 
* 0b10000000: disable USART8
 
* 0b10000000: disable USART8
* 0b11111111: all UART instances are enabled
+
* 0b11111111: all UART instances are enabled.
 
</div>
 
</div>
 
|-
 
|-
Line 111: Line 111:
 
| <span id="USB DP pullup disabling">USB DP pullup disabling</span>
 
| <span id="USB DP pullup disabling">USB DP pullup disabling</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: USB DP pull-up is set
+
* 0: USB DP pull-up is set.
* 1: USB DP pull-up is not set
+
* 1: USB DP pull-up is not set.
 
</div>
 
</div>
 
|-
 
|-
Line 118: Line 118:
 
| <span id="PLL disabling">PLL disabling</span>
 
| <span id="PLL disabling">PLL disabling</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: PLLs for CPU and AXI are enable on cold boot
+
* 0: PLLs for CPU and AXI are enable on cold boot.
* 1: PLLs for CPU and AXI are not enable on cold boot
+
* 1: PLLs for CPU and AXI are not enable on cold boot.
 
</div>
 
</div>
 
|-
 
|-
Line 141: Line 141:
 
| <span id="QSPI non default AFmux">QSPI non default AFmux</span>
 
| <span id="QSPI non default AFmux">QSPI non default AFmux</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: QSPI uses default AFMux
+
* 0: QSPI uses default AFMux.
* 1: QSPI uses AFmux defined in OTP
+
* 1: QSPI uses AFmux defined in OTP.
 
</div>
 
</div>
 
|-
 
|-
Line 148: Line 148:
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
 
| <span id="version monotonic counter">monotonic counter</span>
 
| <span id="version monotonic counter">monotonic counter</span>
| This is an anti rollback monotonic counter : on closed devices, the ROM code checks that it is less or equal to the one stored in the loaded image header.
+
| This is an anti rollback monotonic counter. On closed devices, the ROM code checks if it is less or equal to the one stored in the loaded image header.
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 32
+
* 0b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 32.
* 0b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 31
+
* 0b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 31.
 
* 0b...
 
* 0b...
* 0b00000000000000000000000000000001: monotonic counter value is 1
+
* 0b00000000000000000000000000000001: monotonic counter value is 1.
* 0b00000000000000000000000000000000: monotonic counter value is 0
+
* 0b00000000000000000000000000000000: monotonic counter value is 0.
 
</div>
 
</div>
 
|-
 
|-
| rowspan=8 | 5-7
+
| rowspan=8 | 5
 
| 31-28 (4 bits)
 
| 31-28 (4 bits)
 
| <span id="AFmux configuration">AFmux configuration</span> - port1[3:0]
 
| <span id="AFmux configuration">AFmux configuration</span> - port1[3:0]
Line 242: Line 242:
 
| 3-0 (4 bits)
 
| 3-0 (4 bits)
 
| AFmux configuration - mode0[3:0]
 
| AFmux configuration - mode0[3:0]
  +
| Pin mode
  +
<div class="mw-collapsible mw-collapsed">
  +
* 0: AF; No Pull; Low Speed
  +
* 1: AF; No Pull; Medium Speed
  +
* 2: AF; No Pull; High Speed
  +
* 3: AF; Pull Up; Low Speed
  +
* 4: AF; Pull Up; Medium Speed
  +
* 5: AF; Pull Up;  High Speed
  +
* 6: AF; Pull Down; Low Speed
  +
* 7: AF; Pull Down; Medium Speed
  +
* 8: AF; Pull Down; High Speed
  +
* 9: GPIO Output High
  +
* 10: GPIO Output Low
  +
* 11: GPIO Input
  +
* 12: GPIO open drain; No pull
  +
* 13: GPIO open drain; Pull Up
  +
* 14: GPIO open drain; Pull Down
  +
* 15: GPIO analog mode
  +
</div>
  +
|-
  +
| rowspan=8 | 6
  +
| 31-28 (4 bits)
  +
| <span id="AFmux configuration">AFmux configuration</span> - port3[3:0]
  +
| Bank id
  +
<div class="mw-collapsible mw-collapsed">
  +
* 0: unused
  +
* 1: Bank A
  +
* 2: Bank B
  +
* 3: Bank C
  +
* 4: Bank D
  +
* 5: Bank E
  +
* 6: Bank F
  +
* 7: Bank G
  +
* 8: Bank H
  +
* 9: Bank I
  +
* 10: Bank J
  +
* 11: Bank K
  +
* 12: Bank Z
  +
* 13: not applicable
  +
* 14: not applicable
  +
* 0b1111: Invalid configuration
  +
</div>
  +
|-
  +
| 27-24 (4 bits)
  +
| AFmux configuration - pin3[3:0]
  +
| Pin id
  +
|-
  +
| 23-20 (4 bits)
  +
| AFmux configuration - afmux3[3:0]
  +
| AFmux value
  +
|-
  +
| 19-16 (4 bits)
  +
| AFmux configuration - mode3[3:0]
  +
| Pin mode
  +
<div class="mw-collapsible mw-collapsed">
  +
* 0: AF; No Pull; Low Speed
  +
* 1: AF; No Pull; Medium Speed
  +
* 2: AF; No Pull; High Speed
  +
* 3: AF; Pull Up; Low Speed
  +
* 4: AF; Pull Up; Medium Speed
  +
* 5: AF; Pull Up;  High Speed
  +
* 6: AF; Pull Down; Low Speed
  +
* 7: AF; Pull Down; Medium Speed
  +
* 8: AF; Pull Down; High Speed
  +
* 9: GPIO Output High
  +
* 10: GPIO Output Low
  +
* 11: GPIO Input
  +
* 12: GPIO open drain; No pull
  +
* 13: GPIO open drain; Pull Up
  +
* 14: GPIO open drain; Pull Down
  +
* 15: GPIO analog mode
  +
</div>
  +
|-
  +
| 15-12 (4 bits)
  +
| AFmux configuration - port2[3:0]
  +
| Bank id
  +
<div class="mw-collapsible mw-collapsed">
  +
* 0: unused
  +
* 1: Bank A
  +
* 2: Bank B
  +
* 3: Bank C
  +
* 4: Bank D
  +
* 5: Bank E
  +
* 6: Bank F
  +
* 7: Bank G
  +
* 8: Bank H
  +
* 9: Bank I
  +
* 10: Bank J
  +
* 11: Bank K
  +
* 12: Bank Z
  +
* 13: not applicable
  +
* 14: not applicable
  +
* 0b1111: Invalid configuration
  +
</div>
  +
|-
  +
| 11-8 (4 bits)
  +
| AFmux configuration - pin2[3:0]
  +
| Pin id
  +
|-
  +
| 7-4 (4 bits)
  +
| AFmux configuration - afmux2[3:0]
  +
| AFmux value
  +
|-
  +
| 3-0 (4 bits)
  +
| AFmux configuration - mode2[3:0]
  +
| Pin mode
  +
<div class="mw-collapsible mw-collapsed">
  +
* 0: AF; No Pull; Low Speed
  +
* 1: AF; No Pull; Medium Speed
  +
* 2: AF; No Pull; High Speed
  +
* 3: AF; Pull Up; Low Speed
  +
* 4: AF; Pull Up; Medium Speed
  +
* 5: AF; Pull Up;  High Speed
  +
* 6: AF; Pull Down; Low Speed
  +
* 7: AF; Pull Down; Medium Speed
  +
* 8: AF; Pull Down; High Speed
  +
* 9: GPIO Output High
  +
* 10: GPIO Output Low
  +
* 11: GPIO Input
  +
* 12: GPIO open drain; No pull
  +
* 13: GPIO open drain; Pull Up
  +
* 14: GPIO open drain; Pull Down
  +
* 15: GPIO analog mode
  +
</div>
  +
|-
  +
| rowspan=8 | 7
  +
| 31-28 (4 bits)
  +
| <span id="AFmux configuration">AFmux configuration</span> - port5[3:0]
  +
| Bank id
  +
<div class="mw-collapsible mw-collapsed">
  +
* 0: unused
  +
* 1: Bank A
  +
* 2: Bank B
  +
* 3: Bank C
  +
* 4: Bank D
  +
* 5: Bank E
  +
* 6: Bank F
  +
* 7: Bank G
  +
* 8: Bank H
  +
* 9: Bank I
  +
* 10: Bank J
  +
* 11: Bank K
  +
* 12: Bank Z
  +
* 13: not applicable
  +
* 14: not applicable
  +
* 0b1111: Invalid configuration
  +
</div>
  +
|-
  +
| 27-24 (4 bits)
  +
| AFmux configuration - pin5[3:0]
  +
| Pin id
  +
|-
  +
| 23-20 (4 bits)
  +
| AFmux configuration - afmux5[3:0]
  +
| AFmux value
  +
|-
  +
| 19-16 (4 bits)
  +
| AFmux configuration - mode5[3:0]
  +
| Pin mode
  +
<div class="mw-collapsible mw-collapsed">
  +
* 0: AF; No Pull; Low Speed
  +
* 1: AF; No Pull; Medium Speed
  +
* 2: AF; No Pull; High Speed
  +
* 3: AF; Pull Up; Low Speed
  +
* 4: AF; Pull Up; Medium Speed
  +
* 5: AF; Pull Up;  High Speed
  +
* 6: AF; Pull Down; Low Speed
  +
* 7: AF; Pull Down; Medium Speed
  +
* 8: AF; Pull Down; High Speed
  +
* 9: GPIO Output High
  +
* 10: GPIO Output Low
  +
* 11: GPIO Input
  +
* 12: GPIO open drain; No pull
  +
* 13: GPIO open drain; Pull Up
  +
* 14: GPIO open drain; Pull Down
  +
* 15: GPIO analog mode
  +
</div>
  +
|-
  +
| 15-12 (4 bits)
  +
| AFmux configuration - port4[3:0]
  +
| Bank id
  +
<div class="mw-collapsible mw-collapsed">
  +
* 0: unused
  +
* 1: Bank A
  +
* 2: Bank B
  +
* 3: Bank C
  +
* 4: Bank D
  +
* 5: Bank E
  +
* 6: Bank F
  +
* 7: Bank G
  +
* 8: Bank H
  +
* 9: Bank I
  +
* 10: Bank J
  +
* 11: Bank K
  +
* 12: Bank Z
  +
* 13: not applicable
  +
* 14: not applicable
  +
* 0b1111: Invalid configuration
  +
</div>
  +
|-
  +
| 11-8 (4 bits)
  +
| AFmux configuration - pin4[3:0]
  +
| Pin id
  +
|-
  +
| 7-4 (4 bits)
  +
| AFmux configuration - afmux4[3:0]
  +
| AFmux value
  +
|-
  +
| 3-0 (4 bits)
  +
| AFmux configuration - mode4[3:0]
 
| Pin mode
 
| Pin mode
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
Line 272: Line 482:
 
| FMC NAND parameters storage flag
 
| FMC NAND parameters storage flag
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0b0: NAND parameters are not stored here in OTP and are available via an ‘ONFI’ compliant get parameter command
+
* 0b0: NAND parameters are not stored here in OTP and are available via an ‘ONFI’ compliant get parameter command.
* 0b1: NAND parameters are stored here in OTP
+
* 0b1: NAND parameters are stored here in OTP.
 
</div>
 
</div>
 
<small>Notes:<br>
 
<small>Notes:<br>
 
* serial NAND parameters must always be stored in OTP.  This bit is useless for serial NAND.
 
* serial NAND parameters must always be stored in OTP.  This bit is useless for serial NAND.
 
* there are two NAND parameters banks. The value of [[STM32MP13 OTP mapping#NAND configuration distribution|NAND configuration distribution]] determines the bank to be used.
 
* there are two NAND parameters banks. The value of [[STM32MP13 OTP mapping#NAND configuration distribution|NAND configuration distribution]] determines the bank to be used.
 
 
|-
 
|-
 
| 30-29 (2 bits)
 
| 30-29 (2 bits)
Line 284: Line 493:
 
| FMC or serial NAND page size
 
| FMC or serial NAND page size
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: page size is 2 Kbytes
+
* 0: page size is 2 Kbytes.
* 1: page size is 4 Kbytes
+
* 1: page size is 4 Kbytes.
* 2: page size is 8 Kbytes
+
* 2: page size is 8 Kbytes.
 
* 3: reserved
 
* 3: reserved
 
</div>
 
</div>
Line 295: Line 504:
 
| FMC or serial NAND block size
 
| FMC or serial NAND block size
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: block size is 64 pages
+
* 0: block size is 64 pages.
* 1: block size is 128 pages
+
* 1: block size is 128 pages.
* 2: block size is 256 pages
+
* 2: block size is 256 pages.
 
* 3: reserved
 
* 3: reserved
 
</div>
 
</div>
Line 310: Line 519:
 
| FMC NAND width
 
| FMC NAND width
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: FMC NAND is 8 bits
+
* 0: FMC NAND is 8 bits.
* 1: FMC NAND is 16 bits
+
* 1: FMC NAND is 16 bits.
 
</div>
 
</div>
 
<small>Note: this parameter is part of NAND parameters bank1.</small>
 
<small>Note: this parameter is part of NAND parameters bank1.</small>
Line 319: Line 528:
 
| FMC NAND number of ECC bits
 
| FMC NAND number of ECC bits
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’
+
* 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’.
 
* 1: 1 bit ECC per 512 bytes, Hamming code
 
* 1: 1 bit ECC per 512 bytes, Hamming code
 
* 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
 
* 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
Line 329: Line 538:
 
| 14 (1 bit)
 
| 14 (1 bit)
 
| <span id="spinand needs plane select">spinand needs plane select</span>
 
| <span id="spinand needs plane select">spinand needs plane select</span>
| Serial NAND needs plane select
+
| Serial NAND needs plane select.
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: serial NAND plane select not needed
+
* 0: serial NAND plane select is not needed.
* 1: serial NAND plane select needed
+
* 1: serial NAND plane select is needed.
 
</div>
 
</div>
 
<small>Note: this parameter is part of NAND parameters bank1.</small>
 
<small>Note: this parameter is part of NAND parameters bank1.</small>
Line 343: Line 552:
 
|  <span id="FSBL decryption priority">FSBL decryption priority</span>
 
|  <span id="FSBL decryption priority">FSBL decryption priority</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: use CRYP to priorise speed
+
* 0: use CRYP to prioritize speed.
* 1: use SAES to priorise security
+
* 1: use SAES to prioritize security.
 
</div>
 
</div>
 
|-
 
|-
Line 350: Line 559:
 
|  <span id="SSP success mp13">SSP success</span>
 
|  <span id="SSP success mp13">SSP success</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: SSP is either not started or not finished
+
* 0: SSP is either not started or not finished.
* 1: SSP is finished
+
* 1: SSP is finished.
 
</div>
 
</div>
 
|-
 
|-
Line 357: Line 566:
 
| <span id="SSP request mp13">SSP request</span>
 
| <span id="SSP request mp13">SSP request</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: SSP has never been requested
+
* 0: SSP has never been requested.
* 1: SSP has been requested
+
* 1: SSP has been requested.
 
</div>
 
</div>
 
|-
 
|-
Line 364: Line 573:
 
|  <span id="eMMC 128KB boot partition support">eMMC 128KB boot partition support</span><br>
 
|  <span id="eMMC 128KB boot partition support">eMMC 128KB boot partition support</span><br>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: BootROM does not support eMMC with 128KBytes boot partition
+
* 0: BootROM does not support eMMC with 128KBytes boot partition.
* 1: BootROM supports eMMC with 128KBytes boot partition
+
* 1: BootROM supports eMMC with 128KBytes boot partition.
 
</div>
 
</div>
 
|-
 
|-
Line 372: Line 581:
 
| Disable DDR PLL switch off sequence
 
| Disable DDR PLL switch off sequence
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: DDR DLL switch off sequence enabled  
+
* 0: DDR DLL switch off sequence is enabled.
* 1: DDR DLL switch off sequence disabled
+
* 1: DDR DLL switch off sequence is disabled.
 
</div>
 
</div>
 
|-
 
|-
Line 379: Line 588:
 
| <span id="disable HSE bypass detection">disable HSE bypass detection</span>
 
| <span id="disable HSE bypass detection">disable HSE bypass detection</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: HSE bypass detection enabled
+
* 0: HSE bypass detection is enabled.
* 1: HSE bypass detection disabled
+
* 1: HSE bypass detection is disabled.
 
</div>
 
</div>
 
|-
 
|-
Line 386: Line 595:
 
| <span id="disable HSE frequency autodetection">disable HSE frequency autodetection</span>
 
| <span id="disable HSE frequency autodetection">disable HSE frequency autodetection</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: HSE frequency autodetection enabled
+
* 0: HSE frequency autodetection is enabled.
* 1: HSE frequency autodetection disabled
+
* 1: HSE frequency autodetection is disabled.
 
</div>
 
</div>
 
|-
 
|-
Line 393: Line 602:
 
| <span id="disable ROM code traces">disable ROM code traces</span>
 
| <span id="disable ROM code traces">disable ROM code traces</span>
 
| <div class="mw-collapsible mw-collapsed">
 
| <div class="mw-collapsible mw-collapsed">
* 0: ROM code traces enabled
+
* 0: ROM code traces is enabled.
* 1: ROM code traces disabled
+
* 1: ROM code traces is disabled.
 
</div>
 
</div>
 
|-
 
|-
| rowspan=8 | 10
+
| rowspan=9 | 10
| 31-18 (14 bits)
+
| 31-21 (11 bits)
 
| reserved
 
| reserved
 
|
 
|
  +
|-
  +
| 20-18 (3 bits)
  +
| <span id="rng hctr value">rng hctr value</span>
  +
| RNG HCTR value
  +
<div class="mw-collapsible mw-collapsed">
  +
* 0:default RNG value, RNG_HTCR not modified.
  +
* 1: 0xA2B3 (unsigned long)
  +
* 2: 0xAA74 (unsigned long)
  +
* 3: 0xA6BA (unsigned long)
  +
* 4: 0x9AAE (unsigned long)
  +
* 5: 0x72AC (unsigned long)
  +
* 6: 0xAAC7 (unsigned long)
  +
*Other values: default RNG value, RNG_HTCR not modified.
  +
</div>
 
|-
 
|-
 
| 17-16 (2 bits)
 
| 17-16 (2 bits)
Line 406: Line 629:
 
| NAND parameters bank2 : FMC or serial NAND page size
 
| NAND parameters bank2 : FMC or serial NAND page size
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: page size is 2 Kbytes
+
* 0: page size is 2 Kbytes.
* 1: page size is 4 Kbytes
+
* 1: page size is 4 Kbytes.
* 2: page size is 8 Kbytes
+
* 2: page size is 8 Kbytes.
 
* 3: reserved
 
* 3: reserved
 
</div>
 
</div>
Line 416: Line 639:
 
| NAND parameters bank2 : FMC or serial NAND block size
 
| NAND parameters bank2 : FMC or serial NAND block size
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: block size is 64 pages
+
* 0: block size is 64 pages.
* 1: block size is 128 pages
+
* 1: block size is 128 pages.
* 2: block size is 256 pages
+
* 2: block size is 256 pages.
 
* 3: reserved
 
* 3: reserved
 
</div>
 
</div>
Line 430: Line 653:
 
| NAND parameters bank2 : FMC NAND width
 
| NAND parameters bank2 : FMC NAND width
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: FMC NAND is 8 bits
+
* 0: FMC NAND is 8 bits.
* 1: FMC NAND is 16 bits
+
* 1: FMC NAND is 16 bits.
 
</div>
 
</div>
 
|-
 
|-
Line 438: Line 661:
 
| NAND parameters bank2 : FMC NAND number of ECC bits
 
| NAND parameters bank2 : FMC NAND number of ECC bits
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’
+
* 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’.
 
* 1: 1 bit ECC per 512 bytes, Hamming code
 
* 1: 1 bit ECC per 512 bytes, Hamming code
 
* 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
 
* 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
Line 447: Line 670:
 
| 1 (1 bit)
 
| 1 (1 bit)
 
| <span id="spinand needs plane select bank2">spinand needs plane select</span>
 
| <span id="spinand needs plane select bank2">spinand needs plane select</span>
| NAND parameters bank2 : serial NAND needs plane select
+
| NAND parameters bank2 : serial NAND needs plane select.
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
* 0: serial NAND plane select not needed
+
* 0: serial NAND plane select is not needed.
* 1: serial NAND plane select needed
+
* 1: serial NAND plane select is needed.
 
</div>
 
</div>
 
|-
 
|-
Line 464: Line 687:
 
| -
 
| -
 
| -
 
| -
| See the [[STM32MP13 resources#Reference manuals|reference manual]]
+
| See the [[STM32MP13 resources#Reference manuals|reference manual]].
 
|-
 
|-
 
| rowspan=2 | 22
 
| rowspan=2 | 22
Line 473: Line 696:
 
| 7-0 (8 bits)
 
| 7-0 (8 bits)
 
| <span id="signing key id monotonic counter">signing key id monotonic counter</span>
 
| <span id="signing key id monotonic counter">signing key id monotonic counter</span>
| This is an key revocation monotonic counter used by the ROM to checks that it is less or equal to the active signing key id stored in the loaded image header.
+
| This is a key revocation monotonic counter used by the ROM to check if it is less or equal to the active signing key id stored in the loaded image header.
 
<div class="mw-collapsible mw-collapsed">
 
<div class="mw-collapsible mw-collapsed">
 
* 0b1xxxxxxx: monotonic counter value is 8
 
* 0b1xxxxxxx: monotonic counter value is 8
Line 485: Line 708:
 
| -
 
| -
 
| -
 
| -
| See the [[STM32MP13 resources#Reference manuals|reference manual]]
+
| See the [[STM32MP13 resources#Reference manuals|reference manual]].
 
|-
 
|-
 
| 24
 
| 24
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
| <span id="PKHTH">PKHTH[31:0]</span>
+
| <span id="PKHTH">PKHTH1</span>
| rowspan=8 | The Public Key Hashes Table Hash (PKHTH) is the SHA256 hash of the 8 SHA256 hashes of the 8 ECDSA public keys usable for the Secure boot
+
| rowspan=8 | The Public Key Hashes Table Hash (PKHTH) is the SHA256 hash of the 8 SHA256 hashes of the 8 ECDSA public keys usable for the secure boot.<br>
  +
 
  +
If hash = 01 02 03 04 05 06 07 08… then PKHTH1 = 0x01020304, PKHTH2 = 0x05060708, etc,…
 
|-
 
|-
 
| 25
 
| 25
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
| PKHTH[63:32]
+
| PKHTH2
 
|-
 
|-
 
| 26
 
| 26
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
| PKHTH[95:64]
+
| PKHTH3
 
|-
 
|-
 
| 27
 
| 27
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
| PKHTH[128:96]
+
| PKHTH4
 
|-
 
|-
 
| 28
 
| 28
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
| PKHTH[159:128]
+
| PKHTH5
 
|-
 
|-
 
| 29
 
| 29
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
| PKHTH[191:160]
+
| PKHTH6
 
|-
 
|-
 
| 30
 
| 30
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
| PKHTH[223:192]
+
| PKHTH7
 
|-
 
|-
 
| 31
 
| 31
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
| PKHTH[255:224]
+
| PKHTH8
 
|-
 
|-
 
| 32-55
 
| 32-55
 
| -
 
| -
 
| -
 
| -
| See the [[STM32MP13 resources#Reference manuals|reference manual]]
+
| See the [[STM32MP13 resources#Reference manuals|reference manual]].
 
|-
 
|-
 
| 56
 
| 56
 
| 31-0 (32 bits)
 
| 31-0 (32 bits)
 
| <span id="rma unlock passwd">rma unlock passwd</span>
 
| <span id="rma unlock passwd">rma unlock passwd</span>
| Password required for RMA unlock request
+
| A password is required for RMA unlock request.
 
|-
 
|-
 
| 57
 
| 57
Line 549: Line 774:
 
| -
 
| -
 
| -
 
| -
| See the [[STM32MP13 resources#Reference manuals|reference manual]]
+
| See the [[STM32MP13 resources#Reference manuals|reference manual]].
 
|-
 
|-
 
| 92
 
| 92
Line 571: Line 796:
 
<noinclude>
 
<noinclude>
 
[[Category:STM32MP13 platform configuration|1]]
 
[[Category:STM32MP13 platform configuration|1]]
  +
{{PublicationRequestId | 24644 | 2022-09-26 |}}
 
</noinclude>
 
</noinclude>