Difference between revisions of "SDMMC internal peripheral"

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Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to

  • briefly introduce the SDMMC peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
  • explain, when necessary, how to configure the SDMMC peripheral.

2 Peripheral overview[edit]

The SDMMC peripheral is used to interconnect STM32 MPU to SD memory cards, SDIO and MMC devices.

2.1 Features[edit]

Refer to the STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit]

2.2.1 On STM32MP13x lines Warning.png[edit]

The SDMMC1/2 /3 instances are either non-secure or secure peripherals (under ETZPC control).

Warning white.png Warning
  • When an SDMMC instance is secure internal, the DMA cannot be used to perform data transfers.
  • STMicroelectronics does not provide secure MMC driver (see below chapter)

2.2.2 On STM32MP15x lines More info.png[edit]

The SDMMC1/2/3 instances are non-secure peripherals.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

SDMMC1/2 instances can be used to support memory boot on SD or MMC Flash devices.

The SDMMC3 (only present on STM32MP15x lines More info.png) is not used at boot time.

Info white.png Information
The SDMMC instances are ordered by address in the device tree arch/arm/boot/dts/stm32mp157cstm32mp151.dtsi file for STM32MP15x lines More info.png:
sdmmc3: sdmmc@48004000 {
...
sdmmc1: sdmmc@58005000 {
...
sdmmc2: sdmmc@58007000 {

By default, in OpenSTLinux distribution, sdmmc3 is disabled so the sdmmc1 (SD card on Evaluation boards and Discovery kits) and sdmmc2 (eMMC on Evaluation boards and Wifi on Discovery kits) are respectively aliased to mmc0 and mmc1.
If you enable sdmmc3, it will take the mmc0 alias and the aliases above will shift, so don't forget to update the Linux kernel boot command accordingly!
For instance, 'root=/dev/mmcblk0p6' will become 'root=/dev/mmcblk1p6' to mount the rootfs from the sdmmc1 (SD card) when sdmmc3 is enabled.

3.2 Runtime[edit]

3.2.1 Overview[edit]

On STM32MP13x lines Warning.png only, the SDMMC1/2 /3 instances can be allocated to :

the

the Arm® Cortex®-A7 secure context but this is not supported in OpenSTLinux.

All the SDMMC instances can be allocated to the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the MMC framework

or

.

On STM32MP15x lines More info.png only, SDMMC3 can be allocated to the Arm® Cortex®-M4 to be controlled in STM32Cube MPU Package by STM32Cube SDMMC driver.

Chapter #Peripheral assignment describes which peripheral instance can be assigned to which context.

3.2.2 Software frameworks[edit]

Internal peripherals software table template

| Mass storage | SDMMC | | Linux MMC framework | STM32Cube SDMMC driver | |- |}
3.2.2.1 On STM32MP13x lines Warning.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux
Mass storage SDMMC Linux MMC framework
3.2.2.2 On STM32MP15x lines More info.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Mass storage SDMMC Linux MMC framework STM32Cube SDMMC driver

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

For Linux® kernel configuration, please refer to SDMMC device tree configuration.

3.2.4 Peripheral assignment[edit]

Internal peripherals assignment table template

| rowspan="3" | Mass storage
| rowspan="3" | SDMMC
| SDMMC1
| 
| 
|
|
|-
| SDMMC2
| 
| 
| 
|
|-
| SDMMC3
| 
| 
| 
| Assignment (single choice)
|-

|}

4 How to go further[edit]

5
3.2.4.1 On STM32MP13x lines Warning.png[edit]

Click on the right to expand the legend...

STM32MP13IPsOverview.png

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Mass storage SDMMC SDMMC1 Assignment (single choice)
SDMMC2 Assignment (single choice)
3.2.4.2 On STM32MP15x lines More info.png[edit]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Mass storage SDMMC SDMMC1
SDMMC2
SDMMC3 Assignment (single choice)

4 References[edit]




==<noinclude>{{ApplicableFor
|MPUs list=STM32MP13x, STM32MP15x
|MPUs checklist=STM32MP13x,STM32MP15x
}}</noinclude>


==Article purpose==
The purpose of this article is to
* briefly introduce the SDMMC peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain, when necessary, how to configure the SDMMC peripheral.

==Peripheral overview==
The '''SDMMC''' peripheral is used to interconnect STM32 MPU to SD memory cards, SDIO and MMC devices.

===Features===
Refer to the [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.

===Security support===SDMMC1/2/3 instances are either '''non-secure''' or '''secure''' ==== On {{MicroprocessorDevice | device=13}} ====
The SDMMC1/2 instances are '''secure''' peripherals (under [[ETZPC_internal_peripheral|ETZPC]] control).

{{Warning|
* When an SDMMC instance is secure internal, the DMA cannot be used to perform data transfers. 
* STMicroelectronics does not provide secure MMC driver (see below chapter)}}
==== On {{MicroprocessorDevice | device=15}} ====
The SDMMC1/2/3 instances are '''non-secure''' peripherals.
==Peripheral usage and associated software==
===Boot time===
SDMMC1/2 instances can be used to support memory boot on SD or MMC Flash devices.

The SDMMC3 (only present on {{MicroprocessorDevice | device=15}}) is not used at boot time.
{{Info | The SDMMC instances are ordered by address in the [[Device tree|device tree]] {{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp157cstm32mp151.dtsi}} file for {{MicroprocessorDevice | device=15}}:
 sdmmc3: sdmmc@48004000 {
 ...
 sdmmc1: sdmmc@58005000 {
 ...
 sdmmc2: sdmmc@58007000 {
By default, in [[OpenSTLinux distribution]], '''sdmmc3 is disabled''' so the sdmmc1 (SD card on [[STM32MP157x-EV1_-_hardware_description|Evaluation boards]] and [[STM32MP157x-DKx_-_hardware_description|Discovery kits]]) and sdmmc2 (eMMC on [[STM32MP157x-EV1_-_hardware_description|Evaluation boards]] and Wifi on [[STM32MP157x-DKx_-_hardware_description|Discovery kits]]) are respectively aliased to mmc0 and mmc1.<br>

'''If you enable sdmmc3''', it will take the mmc0 alias and the aliases above will shift, so don't forget to update the Linux kernel boot command accordingly!<br>

For instance, 'root&#61;/dev/mmcblk0p6' will become 'root&#61;/dev/mmcblk1p6' to mount the rootfs from the sdmmc1 (SD card) when sdmmc3 is enabled.}}

===Runtime===

====Overview====SDMMC1/2/3On {{MicroprocessorDevice | device=13}} only, the SDMMC1/2 instances can be allocated to:
* the  the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure context but this is not supported in OpenSTLinux.<br>


All the SDMMC instances can be allocated to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by the [[MMC overview|MMC framework]]

or
* .<br>


On {{MicroprocessorDevice | device=15}} only, SDMMC3 can be allocated to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|STM32Cube SDMMC driver]]
.<br>

Chapter [[#Peripheral assignment]] describes which peripheral instance can be assigned to which context.

====Software frameworks===={{:Internal_===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13 internal peripherals software table template}}
 | Mass storage
 | [[SDMMC internal peripheral|SDMMC]]
 | 
 | [[MMC overview|Linux MMC framework]]
 |
 |-
 |}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_software_table_template}}
 | Mass storage
 | [[SDMMC internal peripheral|SDMMC]]
 | 
 | [[MMC overview|Linux MMC framework]]
 | [[STM32CubeMP1 architecture|STM32Cube SDMMC driver]]
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

For Linux<sup>&reg;</sup> kernel configuration, please refer to [[SDMMC device tree configuration]].

====Peripheral assignment===={{:Internal_===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13_internal_peripherals_assignment_table_template}}<onlyinclude><section begin=stm32mp13 />

 | rowspan="2" | Mass storage
 | rowspan="2" | [[SDMMC internal peripheral|SDMMC]]
 | SDMMC1
 | <span title="assignable peripheral but not supported" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | SDMMC2
 | <span title="assignable peripheral but not supported" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-<section end=stm32mp13 />

 |}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_assignment_table_template}}<section begin=stm32mp15 />

 | rowspan="3" | Mass storage
 | rowspan="3" | [[SDMMC internal peripheral|SDMMC]]
 | SDMMC1
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 |
 |
 |-
 | SDMMC2
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | 
 |
 |-
 | SDMMC3
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-</onlyinclude>

 |}

==How to go further==

==<section end=stm32mp15 />

 |}

==References==<references/>

<noinclude>

{{ArticleBasedOnModel | Internal peripheral article model}}
{{PublicationRequestId | 8316 | 2018-08-06 | AnneJ}}
[[Category:High speed interface peripherals]]
[[Category:Mass storage peripherals]]</noinclude>
(10 intermediate revisions by 3 users not shown)
Line 1: Line 1:
  +
<noinclude>{{ApplicableFor
  +
|MPUs list=STM32MP13x, STM32MP15x
  +
|MPUs checklist=STM32MP13x,STM32MP15x
  +
}}</noinclude>
  +
 
==Article purpose==
 
==Article purpose==
 
The purpose of this article is to
 
The purpose of this article is to
 
* briefly introduce the SDMMC peripheral and its main features
 
* briefly introduce the SDMMC peripheral and its main features
 
* indicate the level of security supported by this hardware block
 
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
+
* explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
 
* explain, when necessary, how to configure the SDMMC peripheral.
 
* explain, when necessary, how to configure the SDMMC peripheral.
   
Line 10: Line 15:
   
 
===Features===
 
===Features===
Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.
+
Refer to the [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.
   
 
===Security support===
 
===Security support===
SDMMC1/2/3 instances are either '''non-secure''' or '''secure''' peripherals (under [[ETZPC_internal_peripheral|ETZPC]] control).
+
==== On {{MicroprocessorDevice | device=13}} ====
 
+
The SDMMC1/2 instances are '''secure''' peripherals (under [[ETZPC_internal_peripheral|ETZPC]] control).
{{Warning|
+
==== On {{MicroprocessorDevice | device=15}} ====
* When an SDMMC instance is secure internal, the DMA cannot be used to perform data transfers.  
+
The SDMMC1/2/3 instances are '''non-secure''' peripherals.
* STMicroelectronics does not provide secure MMC driver (see below chapter)}}
 
   
 
==Peripheral usage and associated software==
 
==Peripheral usage and associated software==
Line 23: Line 27:
 
SDMMC1/2 instances can be used to support memory boot on SD or MMC Flash devices.
 
SDMMC1/2 instances can be used to support memory boot on SD or MMC Flash devices.
   
The SDMMC3 is not used at boot time.
+
The SDMMC3 (only present on {{MicroprocessorDevice | device=15}}) is not used at boot time.
{{Info | The SDMMC instances are ordered by address in the [[Device tree|device tree]] {{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp157c.dtsi}} file:
+
{{Info | The SDMMC instances are ordered by address in the [[Device tree|device tree]] {{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp151.dtsi}} file for {{MicroprocessorDevice | device=15}}:
 
  sdmmc3: sdmmc@48004000 {
 
  sdmmc3: sdmmc@48004000 {
 
  ...
 
  ...
Line 37: Line 41:
   
 
====Overview====
 
====Overview====
SDMMC1/2/3 instances can be allocated to:
+
On {{MicroprocessorDevice | device=13}} only, the SDMMC1/2 instances can be allocated to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure context but this is not supported in OpenSTLinux.<br>
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by the [[MMC overview|MMC framework]]
+
 
or
+
All the SDMMC instances can be allocated to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by the [[MMC overview|MMC framework]].<br>
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|STM32Cube SDMMC driver]]
+
 
  +
On {{MicroprocessorDevice | device=15}} only, SDMMC3 can be allocated to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|STM32Cube SDMMC driver]].<br>
  +
 
 
Chapter [[#Peripheral assignment]] describes which peripheral instance can be assigned to which context.
 
Chapter [[#Peripheral assignment]] describes which peripheral instance can be assigned to which context.
   
 
====Software frameworks====
 
====Software frameworks====
{{:Internal_peripherals_software_table_template}}
+
===== On {{MicroprocessorDevice | device=13}} =====
  +
{{:STM32MP13 internal peripherals software table template}}
  +
| Mass storage
  +
| [[SDMMC internal peripheral|SDMMC]]
  +
|
  +
| [[MMC overview|Linux MMC framework]]
  +
|
  +
|-
  +
|}
  +
===== On {{MicroprocessorDevice | device=15}} =====
  +
{{:STM32MP15_internal_peripherals_software_table_template}}
 
  | Mass storage
 
  | Mass storage
 
  | [[SDMMC internal peripheral|SDMMC]]
 
  | [[SDMMC internal peripheral|SDMMC]]
Line 60: Line 76:
   
 
====Peripheral assignment====
 
====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}
+
===== On {{MicroprocessorDevice | device=13}} =====
<onlyinclude>
+
{{:STM32MP13_internal_peripherals_assignment_table_template}}
  +
<section begin=stm32mp13 />
  +
| rowspan="2" | Mass storage
  +
| rowspan="2" | [[SDMMC internal peripheral|SDMMC]]
  +
| SDMMC1
  +
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
  +
| <span title="assignable peripheral" style="font-size:21px">☐</span>
  +
| Assignment (single choice)
  +
|-
  +
| SDMMC2
  +
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
  +
| <span title="assignable peripheral" style="font-size:21px">☐</span>
  +
| Assignment (single choice)
  +
|-
  +
<section end=stm32mp13 />
  +
|}
  +
===== On {{MicroprocessorDevice | device=15}} =====
  +
{{:STM32MP15_internal_peripherals_assignment_table_template}}
  +
<section begin=stm32mp15 />
 
  | rowspan="3" | Mass storage
 
  | rowspan="3" | Mass storage
 
  | rowspan="3" | [[SDMMC internal peripheral|SDMMC]]
 
  | rowspan="3" | [[SDMMC internal peripheral|SDMMC]]
Line 82: Line 116:
 
  | Assignment (single choice)
 
  | Assignment (single choice)
 
  |-
 
  |-
</onlyinclude>
+
<section end=stm32mp15 />
 
  |}
 
  |}
 
==How to go further==
 
   
 
==References==
 
==References==