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==Article purpose== | ==Article purpose== | ||
The purpose of this article is to | The purpose of this article is to | ||
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* indicate the level of security supported by this hardware block | * indicate the level of security supported by this hardware block | ||
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components | * explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components | ||
* explain, when | * explain, when necessary, how to configure the SDMMC peripheral. | ||
==Peripheral overview== | ==Peripheral overview== | ||
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===Features=== | ===Features=== | ||
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to | Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented. | ||
===Security support=== | ===Security support=== | ||
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===Runtime=== | ===Runtime=== | ||
====Overview==== | ====Overview==== | ||
SDMMC1/2/3 instances can be allocated to: | SDMMC1/2/3 instances can be allocated to: | ||
* the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 non-secure core to be | * the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 non-secure core to be controlled in Linux<sup>®</sup> by the [[MMC overview|MMC framework]] | ||
* the Arm<sup>®</sup> Cortex<sup>®</sup>-M4 to be | or | ||
* the Arm<sup>®</sup> Cortex<sup>®</sup>-M4 to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|STM32Cube SDMMC driver]] | |||
Chapter [[#Peripheral assignment]] describes which peripheral instance can be assigned to which context. | Chapter [[#Peripheral assignment]] describes which peripheral instance can be assigned to which context. | ||
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====Peripheral configuration==== | ====Peripheral configuration==== | ||
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration | The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article. | ||
For Linux<sup>®</sup> kernel configuration, please refer to [[SDMMC device tree configuration]]. | For Linux<sup>®</sup> kernel configuration, please refer to [[SDMMC device tree configuration]]. | ||
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==How to go further== | ==How to go further== | ||
==References== | ==References== | ||
<references/> | <references/> | ||
<noinclude> | |||
{{ArticleBasedOnModel | Internal peripheral article model}} | |||
{{PublicationRequestId | 8316 | 2018-08-06 | AnneJ}} | |||
[[Category:High speed interface peripherals]] | |||
[[Category:Mass storage peripherals]] | |||
</noinclude> | |||
Revision as of 09:56, 8 October 2019
1. Article purpose[edit | edit source]
The purpose of this article is to
- briefly introduce the SDMMC peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
- explain, when necessary, how to configure the SDMMC peripheral.
2. Peripheral overview[edit | edit source]
The SDMMC peripheral is used to interconnect STM32 MPU to SD memory cards, SDIO and MMC devices.
2.1. Features[edit | edit source]
Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.
2.2. Security support[edit | edit source]
SDMMC1/2/3 instances are either non-secure or secure peripherals (under ETZPC control).
3. Peripheral usage and associated software[edit | edit source]
3.1. Boot time[edit | edit source]
SDMMC1/2 instances can be used to support memory boot on SD or MMC Flash devices.
The SDMMC3 is not used at boot time.
 Information
|
The SDMMC instances are ordered by address in the device tree arch/arm/boot/dts/stm32mp157c.dtsi file:
sdmmc3: sdmmc@48004000 {
...
sdmmc1: sdmmc@58005000 {
...
sdmmc2: sdmmc@58007000 {
By default, in OpenSTLinux distribution, sdmmc3 is disabled so the sdmmc1 (SD card on Evaluation boards and Discovery kits) and sdmmc2 (eMMC on Evaluation boards and Wifi on Discovery kits) are respectively aliased to mmc0 and mmc1. |
3.2. Runtime[edit | edit source]
3.2.1. Overview[edit | edit source]
SDMMC1/2/3 instances can be allocated to:
- the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the MMC framework
or
- the Arm® Cortex®-M4 to be controlled in STM32Cube MPU Package by STM32Cube SDMMC driver
Chapter #Peripheral assignment describes which peripheral instance can be assigned to which context.
3.2.2. Software frameworks[edit | edit source]
Internal peripherals software table template
| Mass storage | SDMMC | | Linux MMC framework | STM32Cube SDMMC driver | |- |}
3.2.3. Peripheral configuration[edit | edit source]
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.
For Linux® kernel configuration, please refer to SDMMC device tree configuration.
3.2.4. Peripheral assignment[edit | edit source]
Internal peripherals assignment table template
| rowspan="3" | Mass storage | rowspan="3" | SDMMC | SDMMC1 | | ☐ | | |- | SDMMC2 | | ☐ | | |- | SDMMC3 | | ☐ | ☐ | Assignment (single choice) |-
|}
4. How to go further[edit | edit source]
5. References[edit | edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 