RETRAM internal memory

Applicable for

STM32MP15x lines, STM32MP21x lines, STM32MP23x lines, STM32MP25x lines

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1. Article purpose

The purpose of this article is to:

• briefly introduce the RETRAM internal memory peripheral and its main features,
• indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
• list the software frameworks and drivers managing the peripheral,
• explain how to configure the peripheral.

2. Peripheral overview

The RETRAM internal memory is located in the VSW power domain, allowing it to be supplied during Standby low power mode, and to retain retention firmware or data in Standby mode.

2.1. STM32MP15x lines 

On STM32MP15x lines , the RETRAM internal memory is 64 Kbytes wide and is physically near to the Arm^® Cortex^®-M4 for optimized performance from the core and to execute very quickly by the Cortex-M4 on wake up from Standby mode.

The Cortex-M4 firmware has to be loaded to the RETRAM , starting at address 0x00000000. At least, it must load the part of the firmware containing the vector table, since the Arm^® Cortex^®-M4 reset entry point is address 0x00000004. The rest of the firmware code is loaded into the MCU SRAM. The overall memory mapping is shown in the platform memory mapping section.

While going to Standby low power mode, the RETRAM can remain supplied, so it can preserve a (small) Arm^® Cortex^®-M4 piece of retention firmware that is executed on wake up when the ROM code (running on Arm^® Cortex^®-A7) restarts the Arm^® Cortex^®-M4.

2.2. STM32MP2 series

On STM32MP2 series, the RETRAM internal memory is 128 Kbytes wide and mainly dedicated to the Arm^® Cortex^®-M33 for autonomous wakeup from low power Standby mode.
The Cortex-M33 firmware with low power functions has to be loaded to the "RETRAM" with associated reference CRC by the main processor (TDCID) following the procedure described in the SRAM configuration controller (RAMCFG) chapter of STM32MP25 reference manuals.
On Standby exit, in case of wake up event assigned to Arm^® Cortex^®-M33, the SoC will verify the RETRAM integrity thanks to associated HW ECC and then the Cortex-M33 firmware integrity by checking CRC. In case of success, the SoC will start Cortex-M33 at start address of the RETRAM. Else an error will be generated and sent to main processor or a system reset generated according to system configuration.
Moreover RETRAM is protected by a RISAB memory firewall which allows to define some memory regions with different access rights with a 4kB granularity. Each region can be assigned to the different execution contexts of the plateform.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm^® Cortex^®-A processor(s), and the STM32CubeMPU Package running on the Arm^® Cortex^®-M processor.

3.1. Boot time assignment

3.1.1. On STM32MP15x lines 

At boot time, The RETRAM internal memory can contain the Arm^® Cortex^®-M4 firmware, but could also be dedicated to some other usages.

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 nonsecure (U-Boot)
Core/RAM	RETRAM	RETRAM			☐

3.1.2. On STM32MP2 series

The RETRAM is assigned thanks to RISAB configuration that allows sharing and splitting the memory into different regions. It must be done accordingly to the ecosystem usage, as define for:

• STM32MP21x lines  RETRAM OSTL usage.
• STM32MP23x lines  and STM32MP25x lines  RETRAM OSTL usage.

3.2. Runtime assignment

3.2.1. On STM32MP15x lines 

At runtime the RETRAM can be allocated to:

• the Arm^® Cortex^®-M4 (default) for use with the STM32Cube MPU Package, either for runtime firmware that can be mapped in both RETRAM and MCU SRAM, or for retention firmware that only fits into the RETRAM ,

or

• the Arm^® Cortex^®-A7 secure to be used under OP-TEE,

or

• the Arm^® Cortex^®-A7 non-secure to be used under Linux as reserved memory.

Click on to expand or collapse the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 nonsecure (Linux)	Cortex-M4 (STM32Cube)
Core/RAM	RETRAM	RETRAM	⬚	⬚	☑	Assignment to the Arm® Cortex®-M4 if used

3.2.2. On STM32MP2 series

The RETRAM is assigned thanks to RISAB configuration that allows sharing and splitting the memory into different regions. It must be done accordingly to the ecosystem usage, as define for:

• STM32MP21x lines  RETRAM OSTL usage.
• STM32MP23x lines  and STM32MP25x lines  RETRAM OSTL usage.

4. Software frameworks and drivers

The RETRAM is the minimum (and default) memory for the Arm^® Cortex^®-M4 firmware.The software frameworks and component managing the RETRAM device to host the Arm^® Cortex^®-M4 firmware are listed below.

• Linux^®: Linux reserved memory and Linux remoteproc framework
• OP-TEE: OP-TEE remoteproc source code
• STM32Cube: STM32CubeMP15 Package and STM32CubeMP2 Package
• TF-M:TF-M overview

5. How to assign and configure the peripheral

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

• partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
• HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

Cortex^®

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Cyclic redundancy check calculation unit

Trusted domain compartment identifier - NEW

Error correction capability or Elliptic curve cryptography, meaning depends on context

Board support package

Read only memory

Trusted firmware for Arm^® Cortex^®-A (see TF-A)

Boot loader stage 2

Das U-Boot -- the universal boot loader (see U-Boot)

Random access memory (Early computer memories generally hadserial access. Memories where any given address can be accessed when desired were then called "random access" to distinguish them from the memories where contents can only be accessed in a fixed order. The term is used today for volatile random-acces ssemiconductor memories.)

Linux^® is a registered trademark of Linus Torvalds.

Open portable trusted execution environment

Trusted firmware for Arm^® Cortex^®-M (see TF-M) - NEW

Hardware abstraction layer