Difference between revisions of "MDMA internal peripheral"

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1 Article purpose[edit]

The purpose of this article is to:

  • briefly introduce the MDMA peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
  • explain, when necessary, how to configure the MDMA peripheral.


2 Peripheral overview[edit]

The MDMA is used to perform high-speed data transfers between memory and memory or between peripherals and memory. The MDMA controller features 32 channels, dedicated to DMA transfers. The selection of the device connected to each channel and controlling DMA transfers is directly done by the MDMA.


Among all the requestor lines described in the STM32MP15 reference manuals, DMA channels are the only lines that allow to perform transfers with chained DMA and MDMA (refer to DMA internal peripheral article). As a result, when a device is not connected to the MDMA, it is anyway possible to operate in DMA mode via the DMA controller and chain DMA and MDMA.

2.1 Features[edit]

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit]

The MDMA is a secure peripheral. This means that it performs each transfer in the context of the master that requested it:

  • a transfer requested by the Arm® Cortex®-A7 non-secure core propagates non-secure accesses to the targeted device and/or memory.
  • a transfer requested by Arm Cortex-A7 secure core propagates secure accesses to the targeted device and/or memory.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The MDMA is used at boot time by the FMC.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The MDMA is visible from the Arm Cortex-M4 core. However, it is not supported in this context by STMicroelectronics distribution.


As stated in the 'Security support' chapter above, the MDMA is a secure peripheral. This means that its channels have to be allocated to:

  • the Arm Cortex-A7 non-secure core to be controlled in Linux® by the dmaengine framework

and

  • the Arm Cortex-A7 secure core to be controlled by the MDMA OP-TEE driver

STM32CubeMX allows to distinguish between non-secure and secure channels, among all the available channels.

3.2.2 Software frameworks[edit]

Domain Peripheral Software frameworks Comment
Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core/DMA MDMA OP-TEE MDMA driver Linux dmaengine framework

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

3.2.4 Peripheral assignment[edit]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core/DMA MDMA MDMA Shareable (multiple choices supported)

4 How to go further[edit]

Not applicable

5 References[edit]

<noinclude>

{{ArticleBasedOnModel| [[Internal peripheral article model]]}}
{{ArticleMainWriter|Pierre-YvesM}}
{{ ArticleApprovedVersion|Pierre-YvesM| GeraldB, Pierre-YvesM |No previous approved version| AnneJ - 21Sep'18 - 8859 |  12Oct'18 }}
[[Category:DMA peripherals]]</noinclude>


==Article purpose==
The purpose of this article is to:
* briefly introduce the MDMA peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain, when necessary, how to configure the MDMA peripheral.
{{ReviewsComments| 21Sep'18 ,  AnneJ : this section is mandatory and should not be removed }}

==Peripheral overview==
The '''MDMA''' is used to perform high-speed data transfers between memory and memory or between peripherals and memory. The MDMA controller features 32 channels, dedicated to DMA transfers. The selection of the device connected to each channel and controlling DMA transfers is directly done by the MDMA. <br />
{{ReviewsComments|LPA W905.5, The MDMA controller features 32 channels, dedicated to DMA transfers: confusing --> The MDMA controller features 32 independent channels for transfers ?? <br/>

done by the MDMA --> done in MDMA peripheral (opposite with DMA_MUX I suppose)}}<br />


Among all the requestor lines described in the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]], [[DMA internal peripheral|DMA]] channels are the only lines that allow to perform transfers with chained [[DMA internal peripheral|DMA]] and MDMA (refer to [[DMA internal peripheral]] article). As a result, when a device is not connected to the MDMA, it is anyway possible to operate in DMA mode via the [[DMA internal peripheral|DMA]] controller and chain [[DMA internal peripheral|DMA]] and MDMA. 

===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.<br>


===Security support===
The MDMA is a '''secure''' peripheral. 
This means that it performs each transfer in the context of the master that requested it:
* a transfer requested by the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 '''non-secure''' core propagates '''non-secure accesses''' to the targeted device and/or memory.
* a transfer requested by Arm Cortex-A7 '''secure''' core propagates '''secure accesses''' to the targeted device and/or memory.

==Peripheral usage and associated software==
===Boot time===
The MDMA is used at boot time by the FMC.

===Runtime===
====Overview====
The MDMA is visible from the Arm Cortex-M4 core. However, it is not supported in this context by STMicroelectronics distribution.<br /><br />

{{ReviewsComments| LPA W905.5, STMicroelectronics distribution --> Replace by STM32MPU Embedded Software distribution}}
As stated in the 'Security support' chapter above, the MDMA is a secure peripheral. This means that its channels have to be allocated to: 
* the Arm Cortex-A7 non-secure core to be controlled in Linux<sup>&reg;</sup>  by the [[Dmaengine overview|dmaengine]] framework
and
* the Arm Cortex-A7 secure core to be controlled by the MDMA [[OP-TEE overview|OP-TEE]] driver<br />


[[STM32CubeMX]] allows to distinguish between non-secure and secure channels, among all the available channels.

====Software frameworks====
{{:Internal_peripherals_software_table_template}}
 | Core/DMA
 | [[MDMA internal peripheral|MDMA]]
 | [[OP-TEE_overview|OP-TEE MDMA driver]]
 | [[Dmaengine overview|Linux dmaengine framework]]
 | 
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the  [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}<onlyinclude>

 | rowspan="1" | Core/DMA
 | rowspan="1" | [[MDMA internal peripheral|MDMA]]
 | MDMA
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 |
 | Shareable (multiple choices supported)
 |-</onlyinclude>

 |}

==How to go further==
Not applicable

==References==<references/>
Line 16: Line 16:
 
==Peripheral overview==
 
==Peripheral overview==
 
The '''MDMA''' is used to perform high-speed data transfers between memory and memory or between peripherals and memory. The MDMA controller features 32 channels, dedicated to DMA transfers. The selection of the device connected to each channel and controlling DMA transfers is directly done by the MDMA. <br />
 
The '''MDMA''' is used to perform high-speed data transfers between memory and memory or between peripherals and memory. The MDMA controller features 32 channels, dedicated to DMA transfers. The selection of the device connected to each channel and controlling DMA transfers is directly done by the MDMA. <br />
  +
{{ReviewsComments|LPA W905.5, The MDMA controller features 32 channels, dedicated to DMA transfers: confusing --> The MDMA controller features 32 independent channels for transfers ?? <br/>
  +
done by the MDMA --> done in MDMA peripheral (opposite with DMA_MUX I suppose)}}
 
<br />
 
<br />
   
Line 36: Line 38:
 
====Overview====
 
====Overview====
 
The MDMA is visible from the Arm Cortex-M4 core. However, it is not supported in this context by STMicroelectronics distribution.<br /><br />
 
The MDMA is visible from the Arm Cortex-M4 core. However, it is not supported in this context by STMicroelectronics distribution.<br /><br />
  +
{{ReviewsComments| LPA W905.5, STMicroelectronics distribution --> Replace by STM32MPU Embedded Software distribution}}
   
 
As stated in the 'Security support' chapter above, the MDMA is a secure peripheral. This means that its channels have to be allocated to:  
 
As stated in the 'Security support' chapter above, the MDMA is a secure peripheral. This means that its channels have to be allocated to:  

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