Difference between revisions of "LPTIM internal peripheral"

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1 Article purpose[edit]

The purpose of this article is to

  • briefly introduce the LPTIM peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
  • explain how to configure the LPTIM peripheral

2 Peripheral overview[edit]

The LPTIM peripheral is a single channel low-power timer unit, that can continue to run even during low power modes when it selects a clock source that remains active in RCC.

2.1 Features[edit]

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.

The LPTIM peripheral is available in different configurations, depending on the selected instance :

  • LPTIM1 and LPTIM2 can act as PWM, quadrature encoder[1], external event counter, trigger source for other internal peripherals like: ADC[2], DAC[3], DFSDM[4].
  • LPTIM3 can act as PWM, external event counter, trigger source for other internal peripherals like ADC[2], DFSDM[4].
  • LPTIM4 and LPTIM5 can act as PWM.

2.2 Security support[edit]

The LPTIM is a non-secure peripheral.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The LPTIM is not used at boot time.

3.2 Runtime[edit]

3.2.1 Overview[edit]

LPTIM instances can be allocated to:

  • the Arm® Cortex®-A7 non-secure to be used under Linux® with PWM and/or IIO frameworks., IIO, Counter or/and Clock events frameworks,

or

  • the Arm® Cortex®-M4 to be used with STM32Cube MPU Package with LPTIM HAL driver

3.2.2 Software frameworks[edit]

Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Core/Timers LPTIM Linux PWM framework,
Linux IIO framework,
Counter framework,
Clock events framework
STM32Cube LPTIM driver

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

For Linux kernel configuration, please refer to LPTIM device tree configuration and STM32 LPTIM Linux driver articles.

3.2.4 Peripheral assignment[edit]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core/Timers LPTIM LPTIM1 Assignment (single choice)
LPTIM2 Assignment (single choice)
LPTIM3 Assignment (single choice)
LPTIM4 Assignment (single choice)
LPTIM5 Assignment (single choice)

4 References[edit]



{{EcosystemFlow/Warning| flow=Current}}
====Article purpose==
The purpose of this article is to
* briefly introduce the '''LPTIM''' peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain how to configure the LPTIM peripheral
{{ReviewsComments|-- [[User:Nathalie Sangouard|Nathalie Sangouard]] ([[User talk:Nathalie Sangouard|talk]]) 16:50, 13 November 2020 (CET)<br />Article to be updated to be compliant with ecosystem v2.1.0 (BZ 95795)}}
==Peripheral overview==
The '''LPTIM''' peripheral is a single channel low-power timer unit, that can continue to run even during [[Power overview|low power modes]] when it selects a clock source that remains active in [[RCC internal peripheral|RCC]].

===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.

The LPTIM peripheral is available in different configurations, depending on the selected instance :
* LPTIM1 and LPTIM2 can act as PWM, quadrature encoder<ref name="quadrature_encoder">[https://en.wikipedia.org/wiki/Rotary_encoder#Incremental_rotary_encoder Quadrature encoder]</ref>, external event counter, trigger source for other internal peripherals like: ADC<ref name="adc_internal">[[ADC internal peripheral]]</ref>, DAC<ref name="dac_internal">[[DAC internal peripheral]]</ref>, DFSDM<ref name="dfsdm_internal">[[DFSDM internal peripheral]]</ref>.
* LPTIM3 can act as PWM, external event counter, trigger source for other internal peripherals like ADC<ref name="adc_internal"/>, DFSDM<ref name="dfsdm_internal"/>.
* LPTIM4 and LPTIM5 can act as PWM.

===Security support===
The LPTIM is a '''non-secure''' peripheral.

==Peripheral usage and associated software==
===Boot time===
The LPTIM is not used at boot time.

===Runtime===
====Overview====
LPTIM instances can be allocated to:
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure to be used under Linux<sup>&reg;</sup> with [[PWM overview|PWM]] and/or,  [[IIO overview|IIO]] frameworks., ''Counter'' or/and ''Clock events'' frameworks,

or
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be used with STM32Cube MPU Package with [[STM32CubeMP1 architecture|LPTIM HAL driver]]

====Software frameworks====
{{:Internal_peripherals_software_table_template}}
 | Core/Timers
 | [[LPTIM internal peripheral|LPTIM]]
 | 
 | [[PWM overview|Linux PWM framework]],<br>[[IIO overview|Linux IIO framework]]
,<br>''Counter'' framework,<br>''Clock events'' framework| [[STM32CubeMP1 architecture|STM32Cube LPTIM driver]]
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via [[STM32CubeMX]] tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

For Linux kernel configuration, please refer to [[LPTIM device tree configuration]] and [[LPTIM Linux driver|STM32 LPTIM Linux driver]] articles.

====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}<onlyinclude>

 | rowspan="5" | Core/Timers
 | rowspan="5" | [[LPTIM internal peripheral|LPTIM]]
 | LPTIM1
 |
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | LPTIM2
 |
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | LPTIM3
 |
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | LPTIM4
 |
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | LPTIM5
 |
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-</onlyinclude>

 |}

==References==<references/>

<noinclude>

[[Category:Timers peripherals]]
{{PublicationRequestId | 7894 | 2018-07-03 | AlainF}}
{{ArticleBasedOnModel | Internal peripheral article model}}
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model<br>

[[Category:ToBeAlignedWithModel]]
}}</noinclude>
(One intermediate revision by the same user not shown)
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{{EcosystemFlow/Warning| flow=Current}}
 
 
==Article purpose==
 
==Article purpose==
 
The purpose of this article is to
 
The purpose of this article is to
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* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
 
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
 
* explain how to configure the LPTIM peripheral
 
* explain how to configure the LPTIM peripheral
 
{{ReviewsComments|-- [[User:Nathalie Sangouard|Nathalie Sangouard]] ([[User talk:Nathalie Sangouard|talk]]) 16:50, 13 November 2020 (CET)<br />Article to be updated to be compliant with ecosystem v2.1.0 (BZ 95795)}}
 
   
 
==Peripheral overview==
 
==Peripheral overview==
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====Overview====
 
====Overview====
 
LPTIM instances can be allocated to:
 
LPTIM instances can be allocated to:
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure to be used under Linux<sup>&reg;</sup> with [[PWM overview|PWM]] and/or [[IIO overview|IIO]] frameworks.
+
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure to be used under Linux<sup>&reg;</sup> with [[PWM overview|PWM]][[IIO overview|IIO]], ''Counter'' or/and ''Clock events'' frameworks,
 
or
 
or
 
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be used with STM32Cube MPU Package with [[STM32CubeMP1 architecture|LPTIM HAL driver]]
 
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be used with STM32Cube MPU Package with [[STM32CubeMP1 architecture|LPTIM HAL driver]]
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  | [[LPTIM internal peripheral|LPTIM]]
 
  | [[LPTIM internal peripheral|LPTIM]]
 
  |  
 
  |  
  | [[PWM overview|Linux PWM framework]]<br>[[IIO overview|Linux IIO framework]]
+
  | [[PWM overview|PWM framework]],<br>[[IIO overview|IIO framework]],<br>''Counter'' framework,<br>''Clock events'' framework
 
  | [[STM32CubeMP1 architecture|STM32Cube LPTIM driver]]
 
  | [[STM32CubeMP1 architecture|STM32Cube LPTIM driver]]
 
  |
 
  |