Difference between revisions of "BSEC internal peripheral"

[unchecked revision] [quality revision]
(add an infirmation about upper OTP access exceptions, with link to DT configuration page.)
(add some information about OTP access conditions)
 

1 Article purpose[edit]

The purpose of this article is to

  • briefly introduce the BSEC peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
  • explain, when necessary, how to configure the BSEC peripheral.

2 Peripheral overview[edit]

The BSEC peripheral is used to control an OTP (one time programmable) fuse box, used for on-chip non-volatile storage for device configuration and security parameters.

2.1 Features[edit]

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit]

The BSEC is a secure peripheral.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The BSEC is configured at boot time to set up platform security.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The BSEC instance is a system peripheral and is controlled by the Arm® Cortex®-A7 secure: .

Info.png BSEC lower OTP access can be made available to the Arm® Cortex®-A7 non-secure.Upper OTP access can be managed as exceptions (in Trusted Boot Chain only, using TF-A), via "secure monitor calls", managed by TF-A or by OP-TEE. Please Upper OTP access can be managed as exceptions, please refer to BSEC device tree configuration for more details.

3.2.2 Software frameworks[edit]

Domain Peripheral Software frameworks Comment
Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Security BSEC OP-TEE BSEC driver Linux NVMEM framework

3.2.3 Peripheral configuration[edit]

The configuration is based on Device tree, please refer to BSEC device tree configuration article.
It can be applied by the firmware running in a secure context, done in TF-A or in OP-TEE.
It can also be configured by Linux® kernel, please refer to NVMEM overview article.

3.2.4 Peripheral assignment[edit]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Security BSEC BSEC

4 How to go further[edit]

5 References[edit]



==Article purpose==
The purpose of this article is to
* briefly introduce the BSEC  peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain, when necessary, how to configure the BSEC peripheral.

==Peripheral overview==
The '''BSEC''' peripheral is used to control an OTP (one time programmable) fuse box, used for on-chip non-volatile storage for device configuration and security parameters.<br />


===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.<br>


===Security support===
The BSEC is a '''secure''' peripheral.

==Peripheral usage and associated software==
===Boot time===
The BSEC is configured at boot time to set up platform security.

===Runtime===

====Overview====
The BSEC instance is a system peripheral and is controlled by the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure:.


{{Info|

:* BSEC lower OTP access can be made available to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure.
:* Upper OTP access can be managed as exceptions (in Trusted Boot Chain only, using [[TF-A overview|TF-A]]), , via "secure monitor calls", managed by [[TF-A_overview|TF-A]] or by [[OP-TEE_overview|OP-TEE]]. Please Upper OTP access can be managed as exceptions, please refer to [[BSEC device tree configuration]] for more details.}}

====Software frameworks====
{{:Internal_peripherals_software_table_template}}
 | Security
 | [[BSEC internal peripheral|BSEC]]
 | [[OP-TEE_overview|OP-TEE BSEC driver]]
 | [[NVMEM_overview|Linux NVMEM framework]]
 |
 |
 |-
 |}

====Peripheral configuration====
The configuration is based on [[Device tree]], please refer to [[BSEC device tree configuration]] article.<br/>

It can be applied by the firmware running in a secure context, done in [[TF-A_overview|TF-A]] or in [[OP-TEE_overview|OP-TEE]].<br/>

It can also be configured by Linux<sup>&reg;</sup> kernel, please refer to [[NVMEM overview]] article.

====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}<onlyinclude>

 | rowspan="1" | Security
 | rowspan="1" | [[BSEC internal peripheral|BSEC]]
 | BSEC
 | <span title="system peripheral" style="font-size:21px"></span>

 | <span title="system peripheral" style="font-size:21px"></span>

 |
 |
 |-</onlyinclude>

 |}

==How to go further==

==References==<references/>

<noinclude>

[[Category:Persistent storage peripherals]]
{{ArticleBasedOnModel| Contributors:Internal_peripheral_article_model}}
{{PublicationRequestId | 8892  (PhilipS)  | 2018-10-17}}</noinclude>
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====Overview====
 
====Overview====
The BSEC instance is a system peripheral and is controlled by the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure.
+
The BSEC instance is a system peripheral and is controlled by the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure:
   
{{Info|BSEC lower OTP access can be made available to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure, via "secure monitor calls", managed by [[TF-A_overview|TF-A]] or by [[OP-TEE_overview|OP-TEE]]. Upper OTP access can be managed as exceptions, please refer to [[BSEC device tree configuration]] for more details.}}
+
{{Info|
  +
:* BSEC lower OTP access can be made available to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure.
  +
:* Upper OTP access can be managed as exceptions (in Trusted Boot Chain only, using [[TF-A overview|TF-A]]), via "secure monitor calls", managed by [[TF-A_overview|TF-A]] or by [[OP-TEE_overview|OP-TEE]]. Please refer to [[BSEC device tree configuration]] for more details.}}
   
 
====Software frameworks====
 
====Software frameworks====