TIM internal peripheral

Applicable for

STM32MP13x lines, STM32MP15x lines, STM32MP21x lines, STM32MP23x lines, STM32MP25x lines

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1. Article purpose

The purpose of this article is to:

• briefly introduce the TIM peripheral and its main features,
• indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
• list the software frameworks and drivers managing the peripheral,
• explain how to configure the peripheral.

2. Peripheral overview

The TIM peripheral is a multi-channel timer unit, available in various configurations, depending on the instance used. There are basically following categories: advanced-control timers, general-purpose timers and basic timers.

The TIM can provide: PWM with complementary output and dead-time insertion, break detection, input capture, quadrature encoder interface (typically used for rotary encoders), trigger source for other internal peripherals like: ADC, DFSDM. The full list can be found in Peripherals Interconnect matrix in the reference manual.

The TIM peripheral is available in different configurations, depending on the selected instance :

TIM type	TIM instances	Independent Channels	PWM	External event counter Trigger source	Quadrature encoder
advanced-control timers	TIM1/TIM8	6
general-purpose timers	TIM2/TIM3/TIM4/TIM5	4
	TIM12	2
	TIM13/TIM14	1
	TIM15	2
	TIM16/TIM17	1
basic timers	TIM6/TIM7

Information

Compare to TIM12, TIM13 and TIM14, the configuration of TIM15, TIM16 and TIM17 brings some features that are very useful for motor control (like break function, DMA burst mode control, complementary output with dead-time insertion, ...)

2.1. Additional instances to STM32MP2 series

TIM type	TIM instances	Independent Channels	PWM	External event counter Trigger source	Quadrature encoder
general-purpose timers	TIM10/TIM11	1

2.1.1. Additional instances to STM32MP25x lines 

TIM type	TIM instances	Independent Channels	PWM	External event counter Trigger source	Quadrature encoder
advanced-control timers	TIM20	6

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm^® Cortex^®-A processor(s), and the FwST-M Package running on the Arm^® Cortex^®-M processor.

3.1. Boot time assignment

3.1.1. On STM32MP13x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 nonsecure (U-Boot)
Core/Timers	TIM	TIMx (x = 1 to 8, APB2 group)			☐
		TIMx (x = 2 to 7, APB1 group)			☐
		TIMx (x = 12 to 17, APB6 group)		⬚	☐

3.1.2. On STM32MP15x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 nonsecure (U-Boot)
Core/Timers	TIM	TIMx (x = 2 to 7, 12, 13, 14. APB1 group)			☐
		TIMx (x = 1, 8, 15, 16, 17. APB2 group)			☐

3.1.3. On STM32MP21x lines  and STM32MP23x lines 

3.1.3.1. For A35-TD flavor

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17)		⬚	☐

3.1.3.2. For M33-TD flavor

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation					Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)	Cortex-M33 secure (MCUboot)
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17)		⬚	☐	⬚

3.1.4. On STM32MP25x lines 

3.1.4.1. For A35-TD flavor

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17, 20)		⬚	☐

3.1.4.2. For M33-TD flavor

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation					Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)	Cortex-M33 secure (MCUboot)
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17, 20)		⬚	☐	⬚

3.2. Runtime assignment

3.2.1. On STM32MP13x lines 

TIM12 and/or TIM15 can be allocated to the Arm^® Cortex^®-A7 secure core to be controlled in the secure monitor (OP-TEE).
TIM13, TIM14, TIM16 and TIM17 can also be allocated to the Arm^® Cortex^®-A7 secure context, but it is not supported yet by OpenSTLinux.

Information

RCC owns one prescaler per TIM group corresponding to APB1, APB2 and APB6 buses: TIMG1PRE, TIMG2PRE and TIMG3PRE, respectively. TIMG3PRE is securable in RCC. The allocation to Cortex-A7 contexts should ideally be done on a per group basis to get independent clocking setup on each side, this is why the TIM instances groups are shown in the summary table below.

Click on to expand or collapse the legend...

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 nonsecure (Linux)
Core/Timers	TIM	TIM1 (APB2 group)		☐
		TIM2 (APB1 group)		☐
		TIM3 (APB1 group)		☐
		TIM4 (APB1 group)		☐
		TIM5 (APB1 group)		☐
		TIM6 (APB1 group)		☐
		TIM7 (APB1 group)		☐
		TIM8 (APB2 group)		☐
		TIM12 (APB6 group)	☐	☐	Assignment (single choice) TIM12 or TIM15 can be used for HSI/CSI calibration
		TIM13 (APB6 group)	☐	☐	Assignment (single choice)
		TIM14 (APB6 group)	☐	☐	Assignment (single choice)
		TIM15 (APB6 group)	☐	☐	Assignment (single choice) TIM12 or TIM15 can be used for HSI/CSI calibration
		TIM16 (APB6 group)	☐	☐	Assignment (single choice)
		TIM17 (APB6 group)	☐	☐	Assignment (single choice)

3.2.2. On STM32MP15x lines 

TIM12 and/or TIM15 can be allocated to the Arm^® Cortex^®-A7 secure core to be controlled in the secure monitor (TF-A or OP-TEE).

Information

RCC owns one prescaler per TIM group corresponding to APB1 and APB2 buses: TIMG1PRE and TIMG2PRE, respectively. The allocation to Cortex-A7 or the Cortex-M4 should ideally be done on a per group basis to get independent clocking setup on each side, this is why the TIM instances groups are shown in the summary table below.

Click on to expand or collapse the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 nonsecure (Linux)	Cortex-M4 (STM32Cube)
Core/Timers	TIM	TIM1 (APB2 group)		☐	☐	Assignment (single choice)
		TIM2 (APB1 group)		☐	☐	Assignment (single choice)
		TIM3 (APB1 group)		☐	☐	Assignment (single choice)
		TIM4 (APB1 group)		☐	☐	Assignment (single choice)
		TIM5 (APB1 group)		☐	☐	Assignment (single choice)
		TIM6 (APB1 group)		☐	☐	Assignment (single choice)
		TIM7 (APB1 group)		☐	☐	Assignment (single choice)
		TIM8 (APB2 group)		☐	☐	Assignment (single choice)
		TIM12 (APB1 group)	☐	☐	☐	Assignment (single choice) TIM12 or TIM15 can be used for HSI/CSI calibration
		TIM13 (APB1 group)		☐	☐	Assignment (single choice)
		TIM14 (APB1 group)		☐	☐	Assignment (single choice)
		TIM15 (APB2 group)	☐	☐	☐	Assignment (single choice) TIM12 or TIM15 can be used for HSI/CSI calibration
		TIM16 (APB2 group)		☐	☐	Assignment (single choice)
		TIM17 (APB2 group)		☐	☐	Assignment (single choice)

3.2.3. On STM32MP21x lines  and STM32MP23x lines 

The tables below are applicable to any TD flavor (A35-TD or M33-TD) .

Click on to expand or collapse the legend...

STM32MP21 internal peripherals

STM32MP23 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP21 reference manuals and in STM32MP23 reference manuals.

Domain	Peripheral	Runtime allocation					Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17)	⬚OP-TEE	☐	⬚	☐

3.2.4. On STM32MP25x lines 

The tables below are applicable to any TD flavor (A35-TD or M33-TD) .

Click on to expand or collapse the legend...

STM32MP25 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Runtime allocation						Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)	Cortex-M0+ (STM32Cube)
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17, 20)	⬚OP-TEE	☐	⬚	☐

4. Software frameworks and drivers

Below are listed the software frameworks and drivers managing the TIM peripheral for the embedded software components listed in the above tables.

• Linux^®: PWM, the IIO, and the Counter frameworks
• OP-TEE: OP-TEE TIM driver , to perform HSI and CSI calibrations in RCC
• U-Boot: PWM driver , typically used for a PWM backlight
• STM32Cube: HAL TIM driver

5. How to assign and configure the peripheral

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

• partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
• HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

For Linux kernel configuration, please refer to TIM device tree configuration and TIM_OpenSTLinux_drivers articles.

6. How to go further

STM32 cross-series timer overview application note.

Pulse width modulation

Analog-to-digital converter. The process of converting a sampled analog signal to a digital code that represents the amplitude of the original signal sample.

Digital filter for sigma-delta modulator

Direct memory access

Board support package

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Read only memory

Trusted firmware for Arm^® Cortex^®-A (see TF-A)

Boot loader stage 2

Das U-Boot -- the universal boot loader (see U-Boot)

Arm^® Cortex^®-A35 trusted domain

Arm^® Cortex^®-M33 trusted domain

MCUboot is a secure bootloader for 32-bits microcontrollers (see https://docs.mcuboot.com) - NEW

Reset and clock control

Open portable trusted execution environment

Linux^® is a registered trademark of Linus Torvalds.

High speed internal oscillator (STM32 clock source) or High speed synchronous serial interface (MIPI^® Alliance standard)

Multi speed internal oscillator (STM32 clock source)

Trusted firmware for Arm^® Cortex^®-M (see TF-M) - NEW

Hardware abstraction layer