All the peripherals receive one or several clocks that are generated via RCC internal peripheral. RCC relies on several clocks sources (LSI, LSE, HSI, HSE, MSI), height PLL, and sixty-four FLEXGEN in order to provide adequate input frequencies to all the peripherals. The clock tree covers all the system clock distribution aspects, from the clock sources to the consumer peripherals (internal and external), except clock gating management that is locally controlled by each peripheral driver.
1. Overview[edit | edit source]
The clock tree is managed via RCC internal peripheral hardware block and it is configured at different steps from the Cortex-A35:
- When the device is reset, all RCC registers take their reset values: the height PLL are disabled and most of the clock source selectors are pointing to the HSI.
- The ROM Code configures the minimum clock tree needed to boot on the selected boot device.
- TF-A BL2 has the same strategy as the ROM code, configuring the minimum clock tree needed for its execution, thanks to the configuration given in the device tree.
- OP-TEE completely configures the clock tree as expected, all the way up to Linux, thanks to the configuration given in the device tree.
- Linux may partly modify clock tree at runtime thanks to SCMI clock services provided by OP-TEE secure OS. Information related to SCMI are taken from the device tree:
- Linux binding is available in Documentation/devicetree/bindings/clock/clock-bindings.txt (and surrounding files): 'fixed-clock' compatible, 'clocks' and 'assigned-clocks' properties are important concepts to understand the management of clocks providers/consumers.
2. How to build a clock tree[edit | edit source]
Building a clock tree is quite complex as it needs to take into account the constraints set by each internal and external peripheral, including external clock sources.
We encourage the use of STM32CubeMX to build the clock tree, and avoid having to know all internal peripherals details: the tool allows the selection of the peripherals that will be present on the board, fix the clock sources frequencies and automatically find an optimized clock tree. It is then able to generate the device tree that is directly consumed by the boot chain and the secure OS. Linux kernel will be able to modify clock tree at runtime thanks to SCMI clock services provided by OP-TEE.
3. ST boards clock tree[edit | edit source]
This chapter ensures that all peripherals receive clocks with characteristics compatible with the specification (frequency, duty cycle, precision) on each ST board.
 Information
|
| See How to change the CPU frequency article for more information about the CPU frequency setting (PLL1), including dynamic voltage and frequency scaling (DVFS) configuration. |
3.1. STM32MP257F-EV1 Evaluation board 
case[edit | edit source]
This chapter shows the result of the boot time clock tree set by the FSBL, overlaid by the runtime clock tree set by the Secure OS on STM32MP257F-EV1 Evaluation board .
Linux eventual runtime modifications are not covered here.
3.1.1. Clock tree[edit | edit source]
The following table shows what STM32MP257F-EV1 Evaluation board clock tree looks like, as a result of the boot chain execution with the device tree built with STM32CubeMX.
hardware
clock rate enable
----------------------------------------------------------------
hsi_ck 64000000 Y
ck_flexgen_08 64000000 Y
ck_ker_usart2 64000000 Y
ck_ker_uart4 64000000 N
ck_flexgen_09 64000000 Y
ck_ker_usart3 64000000 N
ck_ker_uart5 64000000 Y
ck_flexgen_19 16000000 Y
ck_ker_usart1 16000000 N
ck_flexgen_20 64000000 Y
ck_ker_usart6 64000000 N
ck_flexgen_21 64000000 Y
ck_ker_uart7 64000000 N
ck_ker_uart8 64000000 N
ck_flexgen_22 64000000 Y
ck_ker_uart9 64000000 N
ck_flexgen_35 16000000 Y
ck_ker_usbtc 16000000 Y
ck_flexgen_50 64000000 Y
ck_ker_fmc 64000000 Y
lsi_ck 32000 Y
msi_ck 16000000 Y
ck_flexgen_39 16000000 Y
ck_ker_lpuart1 16000000 N
hse_ck 40000000 Y
hse_div2_ck 20000000 Y
ck_ker_usb3pciephy 20000000 Y
ck_hse_rtc 40000000 Y
ck_pll2 600000000 Y
ck_pll3 40000000 N
ck_ker_gpu 40000000 N
ck_pll4 1200000000 Y
ck_icn_hs_mcu 400000000 Y
ck_icn_ls_mcu 200000000 Y
ck_icn_apb1 200000000 Y
ck_timg1 200000000 Y
ck_ker_tim2 200000000 Y
ck_ker_tim3 200000000 N
ck_ker_tim4 200000000 N
ck_ker_tim5 200000000 N
ck_ker_tim6 200000000 Y
ck_ker_tim7 200000000 N
ck_ker_tim10 200000000 N
ck_ker_tim11 200000000 N
ck_ker_tim12 200000000 N
ck_ker_tim13 200000000 N
ck_ker_tim14 200000000 N
ck_icn_p_tim2 200000000 Y
ck_icn_p_tim3 200000000 N
ck_icn_p_tim4 200000000 N
ck_icn_p_tim5 200000000 N
ck_icn_p_tim6 200000000 Y
ck_icn_p_tim7 200000000 N
ck_icn_p_tim10 200000000 N
ck_icn_p_tim11 200000000 N
ck_icn_p_tim12 200000000 N
ck_icn_p_tim13 200000000 N
ck_icn_p_tim14 200000000 N
ck_icn_p_lptim1 200000000 N
ck_icn_p_lptim2 200000000 N
ck_icn_p_spi2 200000000 N
ck_icn_p_spi3 200000000 N
ck_icn_p_spdifrx 200000000 N
ck_icn_p_usart2 200000000 Y
ck_icn_p_usart3 200000000 N
ck_icn_p_uart4 200000000 N
ck_icn_p_uart5 200000000 Y
ck_icn_p_i2c1 200000000 Y
ck_icn_p_i2c2 200000000 N
ck_icn_p_i2c3 200000000 N
ck_icn_p_i2c4 200000000 N
ck_icn_p_i2c5 200000000 N
ck_icn_p_i2c6 200000000 N
ck_icn_p_i2c7 200000000 N
ck_icn_p_i3c1 200000000 N
ck_icn_p_i3c2 200000000 N
ck_icn_p_i3c3 200000000 N
ck_icn_apb2 200000000 Y
ck_timg2 200000000 Y
ck_ker_tim1 200000000 N
ck_ker_tim8 200000000 N
ck_ker_tim15 200000000 N
ck_ker_tim16 200000000 N
ck_ker_tim17 200000000 N
ck_ker_tim20 200000000 N
ck_icn_p_tim1 200000000 N
ck_icn_p_tim8 200000000 N
ck_icn_p_tim15 200000000 N
ck_icn_p_tim16 200000000 N
ck_icn_p_tim17 200000000 N
ck_icn_p_tim20 200000000 N
ck_icn_p_sai1 200000000 N
ck_icn_p_sai2 200000000 N
ck_icn_p_sai3 200000000 N
ck_icn_p_sai4 200000000 N
ck_icn_p_usart1 200000000 N
ck_icn_p_usart6 200000000 N
ck_icn_p_uart7 200000000 N
ck_icn_p_uart8 200000000 N
ck_icn_p_uart9 200000000 N
ck_icn_p_fdcan 200000000 N
ck_icn_p_spi1 200000000 N
ck_icn_p_spi4 200000000 N
ck_icn_p_spi5 200000000 N
ck_icn_p_spi6 200000000 N
ck_icn_p_spi7 200000000 N
ck_icn_apb3 200000000 Y
ck_icn_p_bsec 200000000 Y
ck_icn_p_iwdg1 200000000 Y
ck_icn_p_iwdg2 200000000 N
ck_icn_p_iwdg3 200000000 N
ck_icn_p_iwdg4 200000000 N
ck_icn_p_wwdg1 200000000 N
ck_icn_p_vref 200000000 N
ck_icn_p_dts 200000000 Y
ck_icn_p_serc 200000000 Y
ck_icn_p_hdp 200000000 N
ck_icn_p_is2m 200000000 N
ck_icn_apb4 200000000 Y
ck_icn_p_dsi 200000000 N
ck_icn_p_ltdc 200000000 N
ck_icn_p_csi2 200000000 N
ck_icn_p_dcmipp 200000000 N
ck_icn_p_ddrc 200000000 Y
ck_icn_p_ddrcfg 200000000 Y
ck_icn_p_lvds 200000000 N
ck_icn_p_gicv2m 200000000 Y
ck_icn_p_usbtc 200000000 Y
ck_icn_p_busperfm 200000000 N
ck_icn_p_usb3pciephy 200000000 Y
ck_icn_p_stgen 200000000 Y
ck_icn_p_vdec 200000000 N
ck_icn_p_venc 200000000 N
ck_icn_apbdbg 200000000 Y
ck_sys_dbg 200000000 Y
ck_icn_p_stm 200000000 N
ck_icn_p_etr 200000000 N
ck_icn_s_bkpsram 200000000 Y
ck_icn_p_ddrphyc 200000000 Y
ck_icn_p_syscpu1 200000000 Y
ck_icn_p_hpdma1 200000000 Y
ck_icn_p_hpdma2 200000000 Y
ck_icn_p_hpdma3 200000000 Y
ck_icn_p_ipcc1 200000000 Y
ck_icn_p_ipcc2 200000000 Y
ck_icn_p_cci 200000000 N
ck_icn_p_crc 200000000 N
ck_icn_p_ospiiom 200000000 N
ck_icn_p_hash 200000000 N
ck_icn_p_rng 200000000 Y
ck_icn_p_cryp1 200000000 N
ck_icn_p_cryp2 200000000 N
ck_icn_p_saes 200000000 Y
ck_icn_p_pka 200000000 Y
ck_icn_p_gpioa 200000000 Y
ck_icn_p_gpiob 200000000 Y
ck_icn_p_gpioc 200000000 Y
ck_icn_p_gpiod 200000000 Y
ck_icn_p_gpioe 200000000 Y
ck_icn_p_gpiof 200000000 Y
ck_icn_p_gpiog 200000000 Y
ck_icn_p_gpioh 200000000 Y
ck_icn_p_gpioi 200000000 Y
ck_icn_p_gpioj 200000000 Y
ck_icn_p_gpiok 200000000 Y
ck_icn_s_lpsram1 200000000 Y
ck_icn_s_lpsram2 200000000 Y
ck_icn_s_lpsram3 200000000 Y
ck_icn_p_gpioz 200000000 Y
ck_icn_p_lpdma 200000000 N
ck_icn_p_adf1 200000000 N
ck_icn_p_hsem 200000000 N
ck_icn_p_rtc 200000000 Y
ck_icn_p_iwdg5 200000000 N
ck_icn_p_wwdg2 200000000 N
ck_icn_s_stm 200000000 N
ck_icn_p_fmc 200000000 Y
ck_icn_p_eth1 200000000 N
ck_icn_p_ethsw 200000000 N
ck_icn_p_eth2 200000000 Y
ck_icn_p_pcie 200000000 Y
ck_icn_p_adc12 200000000 N
ck_icn_p_adc3 200000000 Y
ck_icn_p_mdf1 200000000 N
ck_icn_p_spi8 200000000 N
ck_icn_p_lpuart1 200000000 N
ck_icn_p_i2c8 200000000 N
ck_icn_p_lptim3 200000000 Y
ck_icn_p_lptim4 200000000 N
ck_icn_p_lptim5 200000000 N
ck_icn_p_risaf4 200000000 Y
ck_icn_p_i3c4 200000000 N
ck_ker_eth1stp 200000000 N
ck_ker_eth2stp 200000000 N
ck_icn_s_sysram 400000000 Y
ck_icn_s_vderam 400000000 Y
ck_icn_s_retram 400000000 Y
ck_icn_s_sram1 400000000 Y
ck_icn_s_sram2 400000000 Y
ck_icn_s_ospi1 400000000 Y
ck_icn_s_ospi2 400000000 Y
ck_icn_p_otfd1 400000000 Y
ck_icn_p_otfd2 400000000 Y
ck_icn_sdmmc 200000000 Y
ck_icn_m_sdmmc1 200000000 N
ck_icn_m_sdmmc2 200000000 N
ck_icn_m_sdmmc3 200000000 N
ck_icn_ddr 600000000 Y
ck_icn_s_ddr 600000000 Y
ck_icn_display 400000000 Y
ck_icn_hsl 300000000 Y
ck_icn_m_usb2ohci 300000000 Y
ck_icn_m_usb2ehci 300000000 Y
ck_icn_m_usb3dr 300000000 Y
ck_icn_nic 400000000 Y
ck_icn_vid 600000000 Y
ck_flexgen_07 100000000 Y
ck_ker_lptim1 100000000 N
ck_ker_lptim2 100000000 N
ck_flexgen_11 200000000 Y
ck_ker_spdifrx 200000000 N
ck_flexgen_12 100000000 Y
ck_ker_i2c1 100000000 Y
ck_ker_i2c2 100000000 N
ck_ker_i3c1 100000000 N
ck_ker_i3c2 100000000 N
ck_flexgen_13 100000000 Y
ck_ker_i2c3 100000000 N
ck_ker_i2c5 100000000 N
ck_ker_i3c3 100000000 N
ck_flexgen_14 100000000 Y
ck_ker_i2c4 100000000 N
ck_ker_i2c6 100000000 N
ck_flexgen_15 100000000 Y
ck_ker_i2c7 100000000 N
ck_flexgen_16 50000000 Y
ck_ker_spi1 50000000 N
ck_flexgen_26 100000000 Y
ck_ker_fdcan 100000000 N
ck_flexgen_34 20000000 Y
ck_flexgen_41 100000000 Y
ck_ker_lptim4 100000000 N
ck_ker_lptim5 100000000 N
ck_flexgen_43 50000000 Y
ck_ker_tsdbg 50000000 Y
ck_flexgen_44 200000000 Y
ck_ker_tpiu 200000000 N
ck_flexgen_45 400000000 Y
ck_icn_m_etr 400000000 N
ck_sys_atb 400000000 Y
ck_flexgen_51 200000000 Y
ck_ker_sdmmc1 200000000 N
ck_flexgen_52 200000000 Y
ck_ker_sdmmc2 200000000 N
ck_flexgen_53 200000000 Y
ck_ker_sdmmc3 200000000 N
ck_flexgen_56 200000000 Y
ck_ker_eth1ptp 200000000 N
ck_ker_eth2ptp 200000000 Y
ck_flexgen_59 600000000 Y
ck_icn_m_gpu 600000000 N
ck_flexgen_60 50000000 Y
ck_ker_ethswref 50000000 N
ck_flexgen_61 150000000 Y
ck_mco1 150000000 N
ck_flexgen_62 150000000 Y
ck_mco2 150000000 N
ck_flexgen_63 400000000 Y
ck_pll5 532000000 Y
ck_flexgen_17 133000000 Y
ck_ker_spi4 133000000 N
ck_ker_spi5 133000000 N
ck_flexgen_18 133000000 Y
ck_ker_spi6 133000000 N
ck_ker_spi7 133000000 N
ck_flexgen_29 266000000 Y
ck_ker_csi2 266000000 N
ck_flexgen_31 26600000 Y
ck_ker_csi2phy 26600000 N
ck_flexgen_32 26600000 Y
ck_ker_lvdsphy 26600000 N
ck_flexgen_36 133000000 Y
ck_ker_i3c4 133000000 N
ck_flexgen_37 133000000 Y
ck_ker_spi8 133000000 N
ck_flexgen_38 133000000 Y
ck_ker_i2c8 133000000 N
ck_flexgen_46 133000000 Y
ck_ker_adc12 133000000 N
ck_flexgen_47 133000000 Y
ck_ker_adc3 133000000 Y
ck_flexgen_48 133000000 Y
ck_ker_ospi1 133000000 Y
ck_flexgen_49 133000000 Y
ck_ker_ospi2 133000000 Y
ck_pll6 125000000 Y
ck_flexgen_54 62500000 Y
ck_ker_eth1 62500000 N
ck_ker_ethsw 62500000 N
ck_flexgen_55 125000000 Y
ck_ker_eth2 125000000 Y
ck_pll7 835511719 Y
ck_flexgen_10 49147748 Y
ck_ker_spi2 49147748 N
ck_ker_spi3 49147748 N
ck_flexgen_23 49147748 Y
ck_ker_mdf1 49147748 N
ck_ker_sai1 49147748 N
ck_flexgen_24 49147748 Y
ck_ker_sai2 49147748 N
ck_flexgen_25 49147748 Y
ck_ker_sai3 49147748 N
ck_ker_sai4 49147748 N
ck_flexgen_42 49147748 Y
ck_ker_adf1 49147748 N
ck_pll8 594000000 Y
ck_flexgen_27 148500000 Y
ck_ker_ltdc 148500000 N
ck_flexgen_28 27000000 Y
clk_phy_dsi 27000000 N
ck_flexgen_30 20000000 Y
ck_ker_csi2txesc 20000000 N
ck_flexgen_33 40000000 Y
ck_ker_stgen 40000000 Y
ck_flexgen_57 20000000 Y
ck_ker_usb2phy1 20000000 Y
ck_flexgen_58 20000000 Y
ck_ker_usb2phy2 20000000 Y
ck_ker_usb2phy2_en 20000000 Y
ck_ker_dts 40000000 Y
lse_ck 32768 Y
ck_flexgen_40 32768 Y
ck_ker_lptim3 32768 Y
ck_rtc 32768 Y
spdifsymb 0 Y
i2sckin 0 Y
txbyteclk 0 Y
clk_lanebyte 0 N
ck_cpu1 1500000000 Y
ck_obs0 0 Y
ck_obs1 0 Y
3.1.2. Device tree[edit | edit source]
As mentioned in previous chapters, RCC configuration is done in two steps, first by the first stage boot loader (FSBL TF-A) and then by the secure OS (OP-TEE).
Here are the corresponding device tree rcc sub node properties in fdts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi consumed by the first stage boot loader (FSBL TF-A) to configure the clock tree required to boot on STM32MP257F-EV1 Evaluation board :
&rcc {
st,busclk = <
DIV_CFG(DIV_LSMCU, 1)
DIV_CFG(DIV_APB1, 0)
DIV_CFG(DIV_APB2, 0)
DIV_CFG(DIV_APB3, 0)
DIV_CFG(DIV_APB4, 0)
DIV_CFG(DIV_APBDBG, 0)
>;
st,flexgen = <
FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0)
FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1)
FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
>;
st,kerclk = <
MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
>;
pll1: st,pll-1 {
st,pll = <&pll1_cfg_1200Mhz>;
pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
};
};
pll2: st,pll-2 {
st,pll = <&pll2_cfg_600Mhz>;
pll2_cfg_600Mhz: pll2-cfg-600Mhz {
cfg = <30 1 1 2>;
src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
};
};
pll4: st,pll-4 {
st,pll = <&pll4_cfg_1200Mhz>;
pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
};
};
pll5: st,pll-5 {
st,pll = <&pll5_cfg_532Mhz>;
pll5_cfg_532Mhz: pll5-cfg-532Mhz {
cfg = <133 5 1 2>;
src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
};
};
};
Here are the corresponding device tree rcc sub node properties in core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi consumed by the secure OS (OP-TEE) to configure the clock tree above:
&rcc {
st,busclk = <
DIV_CFG(DIV_LSMCU, 1)
DIV_CFG(DIV_APB1, 0)
DIV_CFG(DIV_APB2, 0)
DIV_CFG(DIV_APB3, 0)
DIV_CFG(DIV_APB4, 0)
DIV_CFG(DIV_APBDBG, 0)
>;
st,flexgen = <
FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
FLEXGEN_CFG(3, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(6, XBAR_SRC_PLL4, 0, 1)
FLEXGEN_CFG(7, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0)
FLEXGEN_CFG(9, XBAR_SRC_HSI_KER, 0, 0)
FLEXGEN_CFG(10, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(11, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(12, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(13, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(14, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(15, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(16, XBAR_SRC_PLL4, 0, 23)
FLEXGEN_CFG(17, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(18, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 3)
FLEXGEN_CFG(20, XBAR_SRC_HSI_KER, 0, 0)
FLEXGEN_CFG(21, XBAR_SRC_HSI_KER, 0, 0)
FLEXGEN_CFG(22, XBAR_SRC_HSI_KER, 0, 0)
FLEXGEN_CFG(23, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(24, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(25, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(26, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(27, XBAR_SRC_PLL8, 0, 3)
FLEXGEN_CFG(28, XBAR_SRC_PLL8, 0, 21)
FLEXGEN_CFG(29, XBAR_SRC_PLL5, 0, 1)
FLEXGEN_CFG(30, XBAR_SRC_HSE_KER, 0, 1)
FLEXGEN_CFG(31, XBAR_SRC_PLL5, 0, 19)
FLEXGEN_CFG(32, XBAR_SRC_PLL5, 0, 19)
FLEXGEN_CFG(33, XBAR_SRC_PLL4, 0, 23)
FLEXGEN_CFG(34, XBAR_SRC_PLL4, 0, 59)
FLEXGEN_CFG(35, XBAR_SRC_HSI_KER, 0, 3)
FLEXGEN_CFG(36, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(37, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(38, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(39, XBAR_SRC_MSI_KER, 0, 0)
FLEXGEN_CFG(40, XBAR_SRC_LSE, 0, 0)
FLEXGEN_CFG(41, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(42, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(43, XBAR_SRC_PLL4, 0, 23)
FLEXGEN_CFG(44, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(45, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(46, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(47, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(49, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(53, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(54, XBAR_SRC_PLL6, 0, 3)
FLEXGEN_CFG(55, XBAR_SRC_PLL6, 0, 3)
FLEXGEN_CFG(56, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(57, XBAR_SRC_HSE_KER, 0, 1)
FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1)
FLEXGEN_CFG(59, XBAR_SRC_PLL4, 0, 1)
FLEXGEN_CFG(60, XBAR_SRC_PLL4, 0, 23)
FLEXGEN_CFG(61, XBAR_SRC_PLL4, 0, 7)
FLEXGEN_CFG(62, XBAR_SRC_PLL4, 0, 7)
FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
>;
st,kerclk = <
MUX_CFG(MUX_ADC12, MUX_ADC12_FLEX46)
MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
MUX_CFG(MUX_USB3PCIEPHY, MUX_USB3PCIEPHY_HSE)
MUX_CFG(MUX_DSIPHY, MUX_DSIPHY_FLEX28)
MUX_CFG(MUX_DSIBLANE, MUX_DSIBLANE_DSIPHY)
MUX_CFG(MUX_LVDSPHY, MUX_LVDSPHY_FLEX32)
MUX_CFG(MUX_DTS, MUX_DTS_HSE)
MUX_CFG(MUX_RTC, MUX_RTC_LSE)
MUX_CFG(MUX_D3PER, MUX_D3PER_MSI)
MCO_CFG(MCO1, MUX_MCO1_FLEX61, MCO_OFF)
MCO_CFG(MCO2, MUX_MCO2_FLEX62, MCO_OFF)
>;
pll1: st,pll-1 {
st,pll = <&pll1_cfg_1200Mhz>;
pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
};
pll1_cfg_1500Mhz: pll1-cfg-1500Mhz {
cfg = <75 2 1 1>;
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
};
};
pll2: st,pll-2 {
st,pll = <&pll2_cfg_600Mhz>;
pll2_cfg_600Mhz: pll2-cfg-600Mhz {
cfg = <30 1 1 2>;
src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
};
};
pll3: st,pll-3 {
st,pll = <&pll3_cfg_800Mhz>;
pll3_cfg_800Mhz: pll3-cfg-800Mhz {
cfg = <20 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
};
pll3_cfg_900Mhz: pll3-cfg-900Mhz {
cfg = <45 2 1 1>;
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
};
};
pll4: st,pll-4 {
st,pll = <&pll4_cfg_1200Mhz>;
pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
};
};
pll5: st,pll-5 {
st,pll = <&pll5_cfg_532Mhz>;
pll5_cfg_532Mhz: pll5-cfg-532Mhz {
cfg = <133 5 1 2>;
src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
};
};
pll6: st,pll-6 {
st,pll = <&pll6_cfg_500Mhz>;
pll6_cfg_500Mhz: pll6-cfg-500Mhz {
cfg = <25 1 1 2>;
src = <MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>;
};
};
pll7: st,pll-7 {
st,pll = <&pll7_cfg_835_51172Mhz>;
pll7_cfg_835_51172Mhz: pll7-cfg-835-51172Mhz {
cfg = <167 4 1 2>;
src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>;
frac = < 0x1A3337 >;
};
};
pll8: st,pll-8 {
st,pll = <&pll8_cfg_594Mhz>;
pll8_cfg_594Mhz: pll8-cfg-594Mhz {
cfg = <297 5 1 4>;
src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>;
};
};
};
3.2. STM32MP257F-DK Discovery kit case[edit | edit source]
This chapter shows the result of the boot time clock tree set by the FSBL, overlaid by the runtime clock tree set by the Secure OS on STM32MP257F-DK Discovery kit .
3.2.1. Clock tree[edit | edit source]
The STM32MP257F-DK Discovery kit clock tree looks like, as a result of the boot chain execution with the device tree built with STM32CubeMX can be dispalyed with the next command:
cat /sys/kernel/debug/clk/stm32_clk_summary
3.2.2. Device tree[edit | edit source]
As mentioned in previous chapters, RCC configuration is done in two steps, first by the first stage boot loader (FSBL TF-A) and then by the secure OS (OP-TEE), configured by
- the rcc sub node properties in fdts/stm32mp257f-dk-ca35tdcid-rcc.dtsi consumed by the first stage boot loader (FSBL TF-A) to configure the clock tree required to boot on STM32MP257F-EV1 Evaluation board .
- the rcc sub node properties in core/arch/arm/dts/stm32mp257f-dk-ca35tdcid-rcc.dtsi consumed by the secure OS (OP-TEE) to configure the clock tree above.
3.3. STM32MP257F-DK Discovery kit for STM32MP23x lines evaluation 
case[edit | edit source]
The same clock tree is used in STM32MP257F-DK Discovery kit for STM32MP23x lines evaluation device tree files:
- TF-A in fdts/stm32mp235f-dk-ca35tdcid-rcc.dtsi
- OP-TEE in core/arch/arm/dts/stm32mp235f-dk-ca35tdcid-rcc.dtsi ).
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