Registered User m (Assignment tables reviewed with architects) |
Registered User mNo edit summary Tag: 2017 source edit |
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<noinclude>{{ApplicableFor | <noinclude>{{ApplicableFor | ||
|MPUs list=STM32MP13x, STM32MP15x | |MPUs list=STM32MP13x, STM32MP15x, STM32MP21x, STM32MP23x, STM32MP25x | ||
|MPUs checklist=STM32MP13x, STM32MP15x | |MPUs checklist=STM32MP13x, STM32MP15x, STM32MP21x, STM32MP23x, STM32MP25x | ||
}}</noinclude> | }}</noinclude> | ||
==Article purpose== | ==Article purpose== | ||
The purpose of this article is to: | The purpose of this article is to: | ||
Line 12: | Line 11: | ||
==Peripheral overview== | ==Peripheral overview== | ||
The '''RCC''' peripheral is used to | The '''RCC''' peripheral is used to manage the clock and reset generation for the complete circuit. The RCC gets several internal and external oscillators. They are used as clock sources for the hardware blocks, either directly or indirectly, via the PLLs that allow to achieve high frequencies. | ||
The RCC is | The different features of RCC could be assigned to the execution contexts of the platform: | ||
* '''TZEN''' allows to set some RCC registers in secure mode, in particular registers for configuring PLL1 and PLL2, in order to secure a TrustZone perimeter for the Cortex<sup>®</sup>-A7 secure core and its peripherals. | * On {{MicroprocessorDevice | device=13}}, each resource/sub-function is allocated either to the secure world or to the non-secure world via bits in the RCC_SECCFGR register. | ||
* '''MCKPROT''' allows extending the TZEN secure clock control perimeter to PLL3 and to the MCU subsystem, so to the Cortex<sup>®</sup>-M4 and its bus clock. | * On {{MicroprocessorDevice | device=15}}, there are two levels of security, which are controlled via two bits in the RCC_TZCR register (only accessible in secure mode): | ||
:* '''TZEN''' allows to set some RCC registers in secure mode, in particular registers for configuring PLL1 and PLL2, in order to secure a TrustZone perimeter for the Cortex<sup>®</sup>-A7 secure core and its peripherals. | |||
Please note that all RCC registers can be read from | :* '''MCKPROT''' allows extending the TZEN secure clock control perimeter to PLL3 and to the MCU subsystem, so to the Cortex<sup>®</sup>-M4 and its bus clock. | ||
* On {{MicroprocessorDevice | device=2}}, RCC is a RIF-aware peripheral. That means | |||
:* Dedicated RCC features are protected by RIF protection embedded in RCC following peripheral firewall rules described in [[Resource Isolation Framework overview]] | |||
:* Internal peripheral reset and clock gating control inherit from [[RIFSC internal peripheral|RIFSC]] configuration | |||
:Note: | |||
: Clock gating registers of system resources (Internal RAM, RIF-aware peripherals) are protected by RCC RIF protection (no RIFSC inheritance). This allows to manage automatic clock gating according to either processor low power state or system low power state. Indeed, when a peripheral is shared, it should always be available to any execution context at any time. | |||
Please note that all RCC registers can be read from any execution context. | |||
Refer to the [[STM32 MPU resources#Reference manuals|STM32 MPU reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented. | Refer to the [[STM32 MPU resources#Reference manuals|STM32 MPU reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented. | ||
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===Boot time assignment=== | ===Boot time assignment=== | ||
====On {{MicroprocessorDevice | device=1}}==== | ====On {{MicroprocessorDevice | device=1}}==== | ||
The RCC is used by all the [[Boot chain overview|boot components]]: the ROM code, the FSBL, the SSBL and up to the Linux<sup>®</sup> kernel. Each component is able to reset and gate internal peripherals | |||
The RCC is used by all the [[Boot chain overview|boot components]]: the ROM code, the FSBL, the SSBL and up to | |||
FSBL is responsible to make a minimal {{highlight|clock tree}} initialization for loading the next boot stages. | |||
Then the main {{highlight|clock tree}} initialization step is performed by the [[STM32 MPU OP-TEE overview|OP-TEE]] secure OS: it consists in configuring all the input clocks, the PLLs and the clock sources that are selected as kernel clocks for all peripherals. The whole {{highlight|clock tree}} [[#How to assign and configure the peripheral|configuration]] is carried out by the [[Device tree|device tree]] (see [[STM32MP13 clock tree]] and [[STM32MP15 clock tree]]). | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}} | {{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}} | ||
Line 49: | Line 48: | ||
|- | |- | ||
<section end=stm32mp13_boottime /><section end=stm32mp15_boottime /> | <section end=stm32mp13_boottime /><section end=stm32mp15_boottime /> | ||
|} | |||
====On {{MicroprocessorDevice | device=21}}==== | |||
In Cortex-A main processor mode, the RCC is used by all the [[Boot chain overview|boot components]]: the ROM code, the Cortex-A FSBL, the Secure OS, the SSBL and the Linux<sup>®</sup> kernel. Each SW component is able to reset and gate internal peripherals assigned to it. | |||
ROM code clock tree configuration is fixed, mainly based on HSI internal oscillator. The goal is to configure in a safe mode the platform to load, authenticate and execute the FSBL. | |||
The Cortex-A FSBL is responsible to make a minimal {{highlight|clock tree}} initialization for loading the next boot stages. | |||
Then the main {{highlight|clock tree}} initialization step is performed by the [[STM32 MPU OP-TEE overview|OP-TEE]] secure OS: it consists in configuring all the input clocks, the PLLs and the clock sources that are selected as kernel clocks for all peripherals. The whole {{highlight|clock tree}} [[#How to assign and configure the peripheral|configuration]] is carried out by the [[Device tree|device tree]] (see [[STM32MP2 clock tree]]). | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}} | |||
<section begin=stm32mp21_a35_boottime /> | |||
| rowspan="1" | Power & Thermal | |||
| rowspan="1" | [[RCC internal peripheral | RCC]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| RCC | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[RCC internal peripheral#stm32mp21_RCC_a35_boottime_rif | boot time allocation per feature]] | |||
|- | |||
<section end=stm32mp21_a35_boottime /> | |||
|} | |||
<span id="stm32mp21_RCC_a35_boottime_rif"/>The below table shows the possible boot time allocations for the features of the RCC instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime_rif}} | |||
| FCALC | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSRST | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| BOOT_STDB | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| RDCR | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSCLK | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| CPU1_RES | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| CPU2_RES | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| DEBUG_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSRAM_CFGR | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
| | |||
|- | |||
| RETRAM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| BKPSRAM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SRAM1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| HPDMA1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| HPDMA2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| HPDMA3_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| IPCC1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOA_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOB_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOC_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOD_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOE_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOF_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOG_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOH_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOI_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| RTC_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| BSEC_CFGR | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
| | |||
|- | |||
| DDRC_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
| | |||
|- | |||
| SYSCPU1_CFGR | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| | |||
| | |||
|- | |||
| MCO1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| MCO2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| OSPI1_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| FMC_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HSI_MON | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=23}}==== | |||
In Cortex-A main processor mode, the RCC is used by all the [[Boot chain overview|boot components]]: the ROM code, the Cortex-A FSBL, the Secure OS, the SSBL and the Linux<sup>®</sup> kernel. Each SW component is able to reset and gate internal peripherals assigned to it. | |||
ROM code clock tree configuration is fixed, mainly based on HSI internal oscillator. The goal is to configure in a safe mode the platform to load, authenticate and execute the FSBL. | |||
The Cortex-A FSBL is responsible to make a minimal {{highlight|clock tree}} initialization for loading the next boot stages. | |||
Then the main {{highlight|clock tree}} initialization step is performed by the [[STM32 MPU OP-TEE overview|OP-TEE]] secure OS: it consists in configuring all the input clocks, the PLLs and the clock sources that are selected as kernel clocks for all peripherals. The whole {{highlight|clock tree}} [[#How to assign and configure the peripheral|configuration]] is carried out by the [[Device tree|device tree]] (see [[STM32MP2 clock tree]]). | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}} | |||
<section begin=stm32mp23_a35_boottime /> | |||
| rowspan="1" | Power & Thermal | |||
| rowspan="1" | [[RCC internal peripheral | RCC]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| RCC | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[RCC internal peripheral#stm32mp23_RCC_a35_boottime_rif | boot time allocation per feature]] | |||
|- | |||
<section end=stm32mp23_a35_boottime /> | |||
|} | |||
<span id="stm32mp23_RCC_a35_boottime_rif"/>The below table shows the possible boot time allocations for the features of the RCC instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime_rif}} | |||
| FCALC | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSRST | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| BOOT_STDB | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| RDCR | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSCLK | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| CPU1_RES | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| CPU2_RES | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| DEBUG_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSRAM_CFGR | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
| | |||
|- | |||
| VDERAM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| RETRAM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| BKPSRAM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SRAM1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SRAM2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| HPDMA1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| HPDMA2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| HPDMA3_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| IPCC1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| IPCC2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HSEM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| GPIOA_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOB_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOC_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOD_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOE_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOF_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOG_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOH_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOI_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOJ_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOK_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| RTC_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| BSEC_CFGR | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
| | |||
|- | |||
| DDRC_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
| | |||
|- | |||
| PLL3_CFGR | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSCPU1_CFGR | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| | |||
| | |||
|- | |||
| MCO1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| MCO2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| OSPI1_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| OSPI2_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| FMC_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HSI_MON | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=25}}==== | |||
In Cortex-A main processor mode, the RCC is used by all the [[Boot chain overview|boot components]]: the ROM code, the Cortex-A FSBL, the Secure OS, the SSBL and the Linux<sup>®</sup> kernel. Each SW component is able to reset and gate internal peripherals assigned to it. | |||
ROM code clock tree configuration is fixed, mainly based on HSI internal oscillator. The goal is to configure in a safe mode the platform to load, authenticate and execute the FSBL. | |||
The Cortex-A FSBL is responsible to make a minimal {{highlight|clock tree}} initialization for loading the next boot stages. | |||
Then the main {{highlight|clock tree}} initialization step is performed by the [[STM32 MPU OP-TEE overview|OP-TEE]] secure OS: it consists in configuring all the input clocks, the PLLs and the clock sources that are selected as kernel clocks for all peripherals. The whole {{highlight|clock tree}} [[#How to assign and configure the peripheral|configuration]] is carried out by the [[Device tree|device tree]] (see [[STM32MP2 clock tree]]). | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}} | |||
<section begin=stm32mp25_a35_boottime /> | |||
| rowspan="1" | Power & Thermal | |||
| rowspan="1" | [[RCC internal peripheral | RCC]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| RCC | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[RCC internal peripheral#stm32mp25_RCC_a35_boottime_rif | boot time allocation per feature]] | |||
|- | |||
<section end=stm32mp25_a35_boottime /> | |||
|} | |||
<span id="stm32mp25_RCC_a35_boottime_rif"/>The below table shows the possible boot time allocations for the features of the RCC instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime_rif}} | |||
| FCALC | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSRST | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| BOOT_STDB | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| RDCR | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSCLK | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| CPU1_RES | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| CPU2_RES | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| CPU3_RES | |||
| | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| DEBUG_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSRAM_CFGR | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
| | |||
|- | |||
| VDERAM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| RETRAM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| BKPSRAM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SRAM1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SRAM2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| LPSRAM1_CFGR | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| LPSRAM2_CFGR | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| LPSRAM3_CFGR | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| HPDMA1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| HPDMA2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| HPDMA3_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| LPDMA_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| IPCC1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| IPCC2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HSEM_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| GPIOA_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOB_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOC_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOD_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOE_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOF_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOG_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOH_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOI_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOJ_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOK_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| RTC_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| BSEC_CFGR | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
| | |||
|- | |||
| DDRC_CFGR | |||
| | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span> | |||
| | |||
| | |||
|- | |||
| PLL3_CFGR | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSCPU1_CFGR | |||
| | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| | |||
| | |||
|- | |||
| MCO1_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| MCO2_CFGR | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| OSPI1_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| OSPI2_CFGR | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| FMC_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HSI_MON | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |} | ||
===Runtime assignment=== | ===Runtime assignment=== | ||
The Arm<sup>®</sup> Cortex<sup>®</sup>-A7 secure core controls all the secure registers | ====On {{MicroprocessorDevice | device=1}}==== | ||
The Arm<sup>®</sup> Cortex<sup>®</sup>-A7 secure core controls all the secure registers through the [[STM32 MPU OP-TEE_overview|RCC OP-TEE driver]]. The access to some secure registers from the Cortex<sup>®</sup>-A7 non-secure core can be achieved via [[SCMI_overview|SCMI]] requests. | |||
=====On {{MicroprocessorDevice | device=13}}===== | |||
====On {{MicroprocessorDevice | device=13}}==== | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp13_runtime}} | {{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp13_runtime}} | ||
<section begin=stm32mp13_runtime /> | <section begin=stm32mp13_runtime /> | ||
Line 69: | Line 901: | ||
|} | |} | ||
====On {{MicroprocessorDevice | device=15}}==== | =====On {{MicroprocessorDevice | device=15}}===== | ||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp15_runtime}} | {{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp15_runtime}} | ||
<section begin=stm32mp15_runtime /> | <section begin=stm32mp15_runtime /> | ||
Line 81: | Line 913: | ||
|- | |- | ||
<section end=stm32mp15_runtime /> | <section end=stm32mp15_runtime /> | ||
|} | |||
====On {{MicroprocessorDevice | device=21}}==== | |||
In Cortex-A main processor mode, the Cortex-A secure OS [[STM32 MPU OP-TEE overview|OP-TEE]] controls all the RCC system resources, i.e. resources which are shared between execution contexts or between different internal peripherals, like oscillators, PLLs, root clocks or reset and clock gating of RIF-aware peripherals. | |||
The Cortex-A secure OS [[STM32 MPU OP-TEE overview|OP-TEE]] provides [[SCMI overview|SCMI services]] to access system resources. | |||
For [[RIFSC internal peripheral|RIFSC RISUP]] protected internal peripheral, each SW component can directly access RCC registers to control reset and clock gating. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp21_runtime}} | |||
<section begin=stm32mp21_a35_runtime /> | |||
| rowspan="1" | Power & Thermal | |||
| rowspan="1" | [[RCC internal peripheral | RCC]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| RCC | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[RCC internal peripheral#stm32mp21_RCC_a35_runtime_rif | runtime allocation per feature]] | |||
|- | |||
<section end=stm32mp21_a35_runtime /> | |||
|} | |||
<span id="stm32mp21_RCC_a35_runtime_rif"/>The below table shows the possible runtime allocations for the features of the RCC instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp21_runtime_rif}} | |||
| FCALC | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSRST | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| BOOT_STDB | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| RDCR | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| SYSCLK | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| CPU1_RES | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| CPU2_RES | |||
| | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> if TZ_EN | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> if TZ_DIS | |||
| | |||
|- | |||
| DEBUG_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| SYSRAM_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| RETRAM_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| BKPSRAM_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| SRAM1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HPDMA1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HPDMA2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HPDMA3_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| IPCC1_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOA_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOB_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOC_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOD_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOE_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOF_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOG_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOH_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOI_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| RTC_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| BSEC_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| DDRC_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| SYSCPU1_CFGR | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| MCO1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| MCO2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| OSPI1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| FMC_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HSI_MON | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=23}}==== | |||
In Cortex-A main processor mode, the Cortex-A secure OS [[STM32 MPU OP-TEE overview|OP-TEE]] controls all the RCC system resources, i.e. resources which are shared between execution contexts or between different internal peripherals, like oscillators, PLLs, root clocks or reset and clock gating of RIF-aware peripherals. | |||
The Cortex-A secure OS [[STM32 MPU OP-TEE overview|OP-TEE]] provides [[SCMI overview|SCMI services]] to access system resources. | |||
For [[RIFSC internal peripheral|RIFSC RISUP]] protected internal peripheral, each SW component can directly access RCC registers to control reset and clock gating. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp23_runtime}} | |||
<section begin=stm32mp23_a35_runtime /> | |||
| rowspan="1" | Power & Thermal | |||
| rowspan="1" | [[RCC internal peripheral | RCC]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| RCC | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[RCC internal peripheral#stm32mp23_RCC_a35_runtime_rif | runtime allocation per feature]] | |||
|- | |||
<section end=stm32mp23_a35_runtime /> | |||
|} | |||
<span id="stm32mp23_RCC_a35_runtime_rif"/>The below table shows the possible runtime allocations for the features of the RCC instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp23_runtime_rif}} | |||
| FCALC | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSRST | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| BOOT_STDB | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| RDCR | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| SYSCLK | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| CPU1_RES | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
|- | |||
| CPU2_RES | |||
| | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> if TZ_EN | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> if TZ_DIS | |||
| | |||
|- | |||
| DEBUG_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| SYSRAM_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| VDERAM_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| RETRAM_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| BKPSRAM_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| SRAM1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| SRAM2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HPDMA1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HPDMA2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HPDMA3_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| IPCC1_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| IPCC2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HSEM_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOA_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOB_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOC_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOD_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOE_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOF_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOG_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOH_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOI_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOJ_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOK_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| RTC_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| BSEC_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| DDRC_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| PLL3_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| SYSCPU1_CFGR | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| MCO1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| MCO2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| OSPI1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| OSPI2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| FMC_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| HSI_MON | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=25}}==== | |||
In Cortex-A main processor mode, the Cortex-A secure OS [[STM32 MPU OP-TEE overview|OP-TEE]] controls all the RCC system resources, i.e. resources which are shared between execution contexts or between different internal peripherals, like oscillators, PLLs, root clocks or reset and clock gating of RIF-aware peripherals. | |||
The Cortex-A secure OS [[STM32 MPU OP-TEE overview|OP-TEE]] provides [[SCMI overview|SCMI services]] to access system resources. | |||
For [[RIFSC internal peripheral|RIFSC RISUP]] protected internal peripheral, each SW component can directly access RCC registers to control reset and clock gating. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime}} | |||
<section begin=stm32mp25_a35_runtime /> | |||
| rowspan="1" | Power & Thermal | |||
| rowspan="1" | [[RCC internal peripheral | RCC]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| RCC | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[RCC internal peripheral#stm32mp25_RCC_a35_runtime_rif | runtime allocation per feature]] | |||
|- | |||
<section end=stm32mp25_a35_runtime /> | |||
|} | |||
<span id="stm32mp25_RCC_a35_runtime_rif"/>The below table shows the possible runtime allocations for the features of the RCC instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime_rif}} | |||
| FCALC | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
|- | |||
| SYSRST | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| BOOT_STDB | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| RDCR | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| SYSCLK | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| CPU1_RES | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| CPU2_RES | |||
| | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> if TZ_EN | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> if TZ_DIS | |||
| | |||
| | |||
|- | |||
| CPU3_RES | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| DEBUG_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| SYSRAM_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| VDERAM_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| RETRAM_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| BKPSRAM_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| SRAM1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| SRAM2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| LPSRAM1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| LPSRAM2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| LPSRAM3_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| HPDMA1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| HPDMA2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| HPDMA3_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| LPDMA_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| IPCC1_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| IPCC2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| HSEM_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOA_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOB_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOC_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOD_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOE_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOF_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOG_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOH_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOI_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOJ_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOK_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| GPIOZ_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| RTC_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| BSEC_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| DDRC_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br/> <span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| PLL3_CFGR | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
|- | |||
| SYSCPU1_CFGR | |||
| <span title="system peripheral" style="font-size:21px">✓</span><sup>OP-TEE</sup><br/> <span title="system peripheral" style="font-size:21px">✓</span><sup>TF-A BL31</sup> | |||
| | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
| MCO1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
|- | |||
| MCO2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
| | |||
|- | |||
| OSPI1_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| OSPI2_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| FMC_CFGR | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| HSI_MON | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
|} | |} | ||
Line 87: | Line 1,922: | ||
* '''Linux<sup>®</sup>''': [[Reset overview|Reset framework]] and [[Clock overview|Clock framework]] | * '''Linux<sup>®</sup>''': [[Reset overview|Reset framework]] and [[Clock overview|Clock framework]] | ||
* '''OP-TEE''': {{CodeSource | OP-TEE_OS | core/drivers/clk/ | * '''OP-TEE''': drivers in {{CodeSource | OP-TEE_OS | core/drivers/clk/}} | ||
* '''TF-A | * '''TF-A''': drivers in {{CodeSource | TF-A | drivers/st/clk/}} | ||
* '''U-Boot''': {{CodeSource | U-Boot | drivers/clk/stm32/ | * '''U-Boot''': drivers in {{CodeSource | U-Boot | drivers/clk/stm32/}} | ||
* '''STM32Cube''': {{CodeSource | STM32CubeMP1 | Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c| | * '''STM32Cube''': HAL RCC drivers | ||
** {{CodeSource | STM32CubeMP1 | Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c|stm32mp1xx_hal_rcc.c}} | |||
** {{CodeSource | STM32CubeMP2 | Drivers/STM32MP2xx_HAL_Driver/Src/stm32mp2xx_hal_rcc.c|stm32mp2xx_hal_rcc.c}} | |||
See also the [[SCMI overview]]. | |||
==How to assign and configure the peripheral== | ==How to assign and configure the peripheral== | ||
The peripheral assignment can be done via the [[STM32CubeMX]] graphical tool (and manually completed if needed). | The peripheral assignment can be done via the [[STM32CubeMX]] graphical tool (and manually completed if needed). | ||
This tool also helps to configure the peripheral: | This tool also helps to configure the peripheral: | ||
* partial device trees (pin control and clock tree) generation for the OpenSTLinux software components, | * partial device trees (pin control and {{highlight|clock tree}}) generation for the OpenSTLinux software components, | ||
* HAL initialization code generation for the STM32CubeMPU Package. | * HAL initialization code generation for the STM32CubeMPU Package. | ||
The configuration is applied by the firmware running in the context in which the peripheral is assigned. | The configuration is applied by the firmware running in the context in which the peripheral is assigned. | ||
For configuration of '''reset''' part of RCC, refer to [[Reset device tree configuration]]. | |||
For configuration of '''clock''' part of RCC, the [[STM32CubeMX]] tool allows configuring the {{highlight|clock tree}} and integrates all the information documented in the [[STM32 MPU resources#Reference manuals|STM32 MPU reference manuals]]. It is highly recommended to use it to generate your [[Device tree|device tree]] as explained in: | |||
* [[STM32MP13 clock tree]] | |||
* [[STM32MP2 clock tree]] | |||
On {{MicroprocessorDevice | device=15}}, the RCC security level differs for each boards and is defined by RCC compatible in OP-TEE device tree: | |||
* "st,stm32mp1-rcc-secure": sets TZEN to 1 and MCKPROT to 0 | |||
* "st,stm32mp1-rcc": sets TZEN to 0 and MCKPROT to 0 | |||
The STMicroelectronics {{MicroprocessorDevice | device=15}} boards use TZEN=1. | |||
==How to go further== | ==How to go further== |
Latest revision as of 18:31, 3 December 2024
1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the RCC peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The RCC peripheral is used to manage the clock and reset generation for the complete circuit. The RCC gets several internal and external oscillators. They are used as clock sources for the hardware blocks, either directly or indirectly, via the PLLs that allow to achieve high frequencies.
The different features of RCC could be assigned to the execution contexts of the platform:
- On STM32MP13x lines , each resource/sub-function is allocated either to the secure world or to the non-secure world via bits in the RCC_SECCFGR register.
- On STM32MP15x lines , there are two levels of security, which are controlled via two bits in the RCC_TZCR register (only accessible in secure mode):
- TZEN allows to set some RCC registers in secure mode, in particular registers for configuring PLL1 and PLL2, in order to secure a TrustZone perimeter for the Cortex®-A7 secure core and its peripherals.
- MCKPROT allows extending the TZEN secure clock control perimeter to PLL3 and to the MCU subsystem, so to the Cortex®-M4 and its bus clock.
- On STM32MP2 unknown microprocessor device, RCC is a RIF-aware peripheral. That means
- Dedicated RCC features are protected by RIF protection embedded in RCC following peripheral firewall rules described in Resource Isolation Framework overview
- Internal peripheral reset and clock gating control inherit from RIFSC configuration
- Note:
- Clock gating registers of system resources (Internal RAM, RIF-aware peripherals) are protected by RCC RIF protection (no RIFSC inheritance). This allows to manage automatic clock gating according to either processor low power state or system low power state. Indeed, when a peripheral is shared, it should always be available to any execution context at any time.
Please note that all RCC registers can be read from any execution context.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
3.1.1. On STM32MP1 Series[edit | edit source]
The RCC is used by all the boot components: the ROM code, the FSBL, the SSBL and up to the Linux® kernel. Each component is able to reset and gate internal peripherals
FSBL is responsible to make a minimal clock tree initialization for loading the next boot stages. Then the main clock tree initialization step is performed by the OP-TEE secure OS: it consists in configuring all the input clocks, the PLLs and the clock sources that are selected as kernel clocks for all peripherals. The whole clock tree configuration is carried out by the device tree (see STM32MP13 clock tree and STM32MP15 clock tree).
Click on the right to expand the legend...
Domain | Peripheral | Boot time allocation | Comment | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
Power & Thermal | RCC | RCC | ✓ | ✓ | ✓ |
3.1.2. On STM32MP21 unknown microprocessor device[edit | edit source]
In Cortex-A main processor mode, the RCC is used by all the boot components: the ROM code, the Cortex-A FSBL, the Secure OS, the SSBL and the Linux® kernel. Each SW component is able to reset and gate internal peripherals assigned to it.
ROM code clock tree configuration is fixed, mainly based on HSI internal oscillator. The goal is to configure in a safe mode the platform to load, authenticate and execute the FSBL.
The Cortex-A FSBL is responsible to make a minimal clock tree initialization for loading the next boot stages. Then the main clock tree initialization step is performed by the OP-TEE secure OS: it consists in configuring all the input clocks, the PLLs and the clock sources that are selected as kernel clocks for all peripherals. The whole clock tree configuration is carried out by the device tree (see STM32MP2 clock tree).
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Power & Thermal | RCC | RCC | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature |
The below table shows the possible boot time allocations for the features of the RCC instance.
Feature | Boot time allocation | Comment | ||
---|---|---|---|---|
Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | ||
FCALC | ⬚ | |||
SYSRST | ✓ | ⬚ | ||
BOOT_STDB | ✓ | ⬚ | ||
RDCR | ✓ | ⬚ | ||
SYSCLK | ✓ | ⬚ | ||
CPU1_RES | ✓ | ✓ | ⬚ | |
CPU2_RES | ||||
DEBUG_CFGR | ☐ | ⬚ | ||
SYSRAM_CFGR | ✓ | ☑ | ||
RETRAM_CFGR | ⬚ | ⬚ | ||
BKPSRAM_CFGR | ⬚ | ⬚ | ||
SRAM1_CFGR | ⬚ | ⬚ | ||
HPDMA1_CFGR | ⬚ | ⬚ | ||
HPDMA2_CFGR | ⬚ | ⬚ | ||
HPDMA3_CFGR | ⬚ | ⬚ | ||
IPCC1_CFGR | ⬚ | ☐ | ||
GPIOA_CFGR | ☑ | ☐ | ||
GPIOB_CFGR | ☑ | ☐ | ||
GPIOC_CFGR | ☑ | ☐ | ||
GPIOD_CFGR | ☑ | ☐ | ||
GPIOE_CFGR | ☑ | ☐ | ||
GPIOF_CFGR | ☑ | ☐ | ||
GPIOG_CFGR | ☑ | ☐ | ||
GPIOH_CFGR | ☑ | ☐ | ||
GPIOI_CFGR | ☑ | ☐ | ||
GPIOZ_CFGR | ☑ | ☐ | ||
RTC_CFGR | ☐ | ☐ | ||
BSEC_CFGR | ✓ | ☑ | ||
DDRC_CFGR | ☑ | |||
SYSCPU1_CFGR | ✓ | |||
MCO1_CFGR | ⬚ | ⬚ | ||
MCO2_CFGR | ⬚ | ⬚ | ||
OSPI1_CFGR | ☐ | ☐ | ||
FMC_CFGR | ☐ | ☐ | ☐ | |
HSI_MON | ⬚ | ☐ |
3.1.3. On STM32MP23 unknown microprocessor device[edit | edit source]
In Cortex-A main processor mode, the RCC is used by all the boot components: the ROM code, the Cortex-A FSBL, the Secure OS, the SSBL and the Linux® kernel. Each SW component is able to reset and gate internal peripherals assigned to it.
ROM code clock tree configuration is fixed, mainly based on HSI internal oscillator. The goal is to configure in a safe mode the platform to load, authenticate and execute the FSBL.
The Cortex-A FSBL is responsible to make a minimal clock tree initialization for loading the next boot stages. Then the main clock tree initialization step is performed by the OP-TEE secure OS: it consists in configuring all the input clocks, the PLLs and the clock sources that are selected as kernel clocks for all peripherals. The whole clock tree configuration is carried out by the device tree (see STM32MP2 clock tree).
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Power & Thermal | RCC | RCC | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature |
The below table shows the possible boot time allocations for the features of the RCC instance.
Feature | Boot time allocation | Comment | ||
---|---|---|---|---|
Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | ||
FCALC | ⬚ | |||
SYSRST | ✓ | ⬚ | ||
BOOT_STDB | ✓ | ⬚ | ||
RDCR | ✓ | ⬚ | ||
SYSCLK | ✓ | ⬚ | ||
CPU1_RES | ✓ | ✓ | ⬚ | |
CPU2_RES | ||||
DEBUG_CFGR | ☐ | ⬚ | ||
SYSRAM_CFGR | ✓ | ☑ | ||
VDERAM_CFGR | ⬚ | ⬚ | ||
RETRAM_CFGR | ⬚ | ⬚ | ||
BKPSRAM_CFGR | ⬚ | ⬚ | ||
SRAM1_CFGR | ⬚ | ⬚ | ||
SRAM2_CFGR | ⬚ | ⬚ | ||
HPDMA1_CFGR | ⬚ | ⬚ | ||
HPDMA2_CFGR | ⬚ | ⬚ | ||
HPDMA3_CFGR | ⬚ | ⬚ | ||
IPCC1_CFGR | ⬚ | ☐ | ||
IPCC2_CFGR | ⬚ | ☐ | ||
HSEM_CFGR | ⬚ | ⬚ | ||
GPIOA_CFGR | ☑ | ☐ | ||
GPIOB_CFGR | ☑ | ☐ | ||
GPIOC_CFGR | ☑ | ☐ | ||
GPIOD_CFGR | ☑ | ☐ | ||
GPIOE_CFGR | ☑ | ☐ | ||
GPIOF_CFGR | ☑ | ☐ | ||
GPIOG_CFGR | ☑ | ☐ | ||
GPIOH_CFGR | ☑ | ☐ | ||
GPIOI_CFGR | ☑ | ☐ | ||
GPIOJ_CFGR | ☑ | ☐ | ||
GPIOK_CFGR | ☑ | ☐ | ||
GPIOZ_CFGR | ☑ | ☐ | ||
RTC_CFGR | ☐ | ☐ | ||
BSEC_CFGR | ✓ | ☑ | ||
DDRC_CFGR | ☑ | |||
PLL3_CFGR | ⬚ | |||
SYSCPU1_CFGR | ✓ | |||
MCO1_CFGR | ⬚ | ⬚ | ||
MCO2_CFGR | ⬚ | ⬚ | ||
OSPI1_CFGR | ☐ | ☐ | ||
OSPI2_CFGR | ☐ | ☐ | ||
FMC_CFGR | ☐ | ☐ | ☐ | |
HSI_MON | ⬚ | ☐ |
3.1.4. On STM32MP25 unknown microprocessor device[edit | edit source]
In Cortex-A main processor mode, the RCC is used by all the boot components: the ROM code, the Cortex-A FSBL, the Secure OS, the SSBL and the Linux® kernel. Each SW component is able to reset and gate internal peripherals assigned to it.
ROM code clock tree configuration is fixed, mainly based on HSI internal oscillator. The goal is to configure in a safe mode the platform to load, authenticate and execute the FSBL.
The Cortex-A FSBL is responsible to make a minimal clock tree initialization for loading the next boot stages. Then the main clock tree initialization step is performed by the OP-TEE secure OS: it consists in configuring all the input clocks, the PLLs and the clock sources that are selected as kernel clocks for all peripherals. The whole clock tree configuration is carried out by the device tree (see STM32MP2 clock tree).
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Power & Thermal | RCC | RCC | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature |
The below table shows the possible boot time allocations for the features of the RCC instance.
Feature | Boot time allocation | Comment | ||
---|---|---|---|---|
Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | ||
FCALC | ⬚ | |||
SYSRST | ✓ | ⬚ | ||
BOOT_STDB | ✓ | ⬚ | ||
RDCR | ✓ | ⬚ | ||
SYSCLK | ✓ | ⬚ | ||
CPU1_RES | ✓ | ✓ | ⬚ | |
CPU2_RES | ||||
CPU3_RES | ☐ | |||
DEBUG_CFGR | ☐ | ⬚ | ||
SYSRAM_CFGR | ✓ | ☑ | ||
VDERAM_CFGR | ⬚ | ⬚ | ||
RETRAM_CFGR | ⬚ | ⬚ | ||
BKPSRAM_CFGR | ⬚ | ⬚ | ||
SRAM1_CFGR | ⬚ | ⬚ | ||
SRAM2_CFGR | ⬚ | ⬚ | ||
LPSRAM1_CFGR | ⬚ | |||
LPSRAM2_CFGR | ⬚ | |||
LPSRAM3_CFGR | ⬚ | |||
HPDMA1_CFGR | ⬚ | ⬚ | ||
HPDMA2_CFGR | ⬚ | ⬚ | ||
HPDMA3_CFGR | ⬚ | ⬚ | ||
LPDMA_CFGR | ⬚ | ⬚ | ||
IPCC1_CFGR | ⬚ | ☐ | ||
IPCC2_CFGR | ⬚ | ☐ | ||
HSEM_CFGR | ⬚ | ⬚ | ||
GPIOA_CFGR | ☑ | ☐ | ||
GPIOB_CFGR | ☑ | ☐ | ||
GPIOC_CFGR | ☑ | ☐ | ||
GPIOD_CFGR | ☑ | ☐ | ||
GPIOE_CFGR | ☑ | ☐ | ||
GPIOF_CFGR | ☑ | ☐ | ||
GPIOG_CFGR | ☑ | ☐ | ||
GPIOH_CFGR | ☑ | ☐ | ||
GPIOI_CFGR | ☑ | ☐ | ||
GPIOJ_CFGR | ☑ | ☐ | ||
GPIOK_CFGR | ☑ | ☐ | ||
GPIOZ_CFGR | ☑ | ☐ | ||
RTC_CFGR | ☐ | ☐ | ||
BSEC_CFGR | ✓ | ☑ | ||
DDRC_CFGR | ☑ | |||
PLL3_CFGR | ⬚ | |||
SYSCPU1_CFGR | ✓ | |||
MCO1_CFGR | ⬚ | ⬚ | ||
MCO2_CFGR | ⬚ | ⬚ | ||
OSPI1_CFGR | ☐ | ☐ | ||
OSPI2_CFGR | ☐ | ☐ | ||
FMC_CFGR | ☐ | ☐ | ☐ | |
HSI_MON | ⬚ | ☐ |
3.2. Runtime assignment[edit | edit source]
3.2.1. On STM32MP1 Series[edit | edit source]
The Arm® Cortex®-A7 secure core controls all the secure registers through the RCC OP-TEE driver. The access to some secure registers from the Cortex®-A7 non-secure core can be achieved via SCMI requests.
3.2.1.1. On STM32MP13x lines [edit | edit source]
Click on the right to expand the legend...
Domain | Peripheral | Runtime allocation | Comment | ||
---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
Power & Thermal | RCC | RCC | ✓ | ✓ |
3.2.1.2. On STM32MP15x lines [edit | edit source]
Click on the right to expand the legend...
Domain | Peripheral | Runtime allocation | Comment | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
Power & Thermal | RCC | RCC | ✓ | ✓ | ✓ |
3.2.2. On STM32MP21 unknown microprocessor device[edit | edit source]
In Cortex-A main processor mode, the Cortex-A secure OS OP-TEE controls all the RCC system resources, i.e. resources which are shared between execution contexts or between different internal peripherals, like oscillators, PLLs, root clocks or reset and clock gating of RIF-aware peripherals. The Cortex-A secure OS OP-TEE provides SCMI services to access system resources. For RIFSC RISUP protected internal peripheral, each SW component can directly access RCC registers to control reset and clock gating.
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Power & Thermal | RCC | RCC | ☐ | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the RCC instance.
Feature | Runtime allocation | Comment | |||
---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | ||
FCALC | ☑OP-TEE | ⬚ | ☐ | ⬚ | |
SYSRST | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
BOOT_STDB | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
RDCR | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
SYSCLK | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
CPU1_RES | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
CPU2_RES | ☐ if TZ_EN | ☐ if TZ_DIS | |||
DEBUG_CFGR | ☑OP-TEE | ☐ | ☐ | ☐ | |
SYSRAM_CFGR | ☑OP-TEE ☑TF-A BL31 |
||||
RETRAM_CFGR | ☐OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
BKPSRAM_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
SRAM1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
HPDMA1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
HPDMA2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
HPDMA3_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
IPCC1_CFGR | ☑OP-TEE | ☐ | ☐ | ☐ | |
GPIOA_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOB_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOC_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOD_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOE_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOF_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOG_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOH_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOI_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOZ_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
RTC_CFGR | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ | |
BSEC_CFGR | ☑OP-TEE ☑TF-A BL31 |
||||
DDRC_CFGR | ☑OP-TEE ☑TF-A BL31 |
||||
SYSCPU1_CFGR | ✓OP-TEE ✓TF-A BL31 |
||||
MCO1_CFGR | ☐OP-TEE | ⬚ | ☐ | ⬚ | |
MCO2_CFGR | ☐OP-TEE | ⬚ | ☐ | ⬚ | |
OSPI1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
FMC_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
HSI_MON | ☑OP-TEE | ☐ | ☐ | ☐ |
3.2.3. On STM32MP23 unknown microprocessor device[edit | edit source]
In Cortex-A main processor mode, the Cortex-A secure OS OP-TEE controls all the RCC system resources, i.e. resources which are shared between execution contexts or between different internal peripherals, like oscillators, PLLs, root clocks or reset and clock gating of RIF-aware peripherals. The Cortex-A secure OS OP-TEE provides SCMI services to access system resources. For RIFSC RISUP protected internal peripheral, each SW component can directly access RCC registers to control reset and clock gating.
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Power & Thermal | RCC | RCC | ☐ | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the RCC instance.
Feature | Runtime allocation | Comment | |||
---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | ||
FCALC | ☑OP-TEE | ⬚ | ☐ | ⬚ | |
SYSRST | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
BOOT_STDB | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
RDCR | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
SYSCLK | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
CPU1_RES | ✓OP-TEE ✓TF-A BL31 |
⬚ | |||
CPU2_RES | ☐ if TZ_EN | ☐ if TZ_DIS | |||
DEBUG_CFGR | ☑OP-TEE | ☐ | ☐ | ☐ | |
SYSRAM_CFGR | ☑OP-TEE ☑TF-A BL31 |
||||
VDERAM_CFGR | ☐OP-TEE | ☐ | ⬚ | ☐ | |
RETRAM_CFGR | ☐OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
BKPSRAM_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
SRAM1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
SRAM2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
HPDMA1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
HPDMA2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
HPDMA3_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
IPCC1_CFGR | ☑OP-TEE | ☐ | ☐ | ☐ | |
IPCC2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
HSEM_CFGR | ☑OP-TEE | ☐ | ⬚ | ☐ | |
GPIOA_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOB_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOC_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOD_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOE_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOF_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOG_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOH_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOI_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOJ_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOK_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOZ_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | |
RTC_CFGR | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ | |
BSEC_CFGR | ☑OP-TEE ☑TF-A BL31 |
||||
DDRC_CFGR | ☑OP-TEE ☑TF-A BL31 |
||||
PLL3_CFGR | ☑OP-TEE | ⬚ | ☐ | ⬚ | |
SYSCPU1_CFGR | ✓OP-TEE ✓TF-A BL31 |
||||
MCO1_CFGR | ☐OP-TEE | ⬚ | ☐ | ⬚ | |
MCO2_CFGR | ☐OP-TEE | ⬚ | ☐ | ⬚ | |
OSPI1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
OSPI2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
FMC_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | |
HSI_MON | ☑OP-TEE | ☐ | ☐ | ☐ |
3.2.4. On STM32MP25 unknown microprocessor device[edit | edit source]
In Cortex-A main processor mode, the Cortex-A secure OS OP-TEE controls all the RCC system resources, i.e. resources which are shared between execution contexts or between different internal peripherals, like oscillators, PLLs, root clocks or reset and clock gating of RIF-aware peripherals. The Cortex-A secure OS OP-TEE provides SCMI services to access system resources. For RIFSC RISUP protected internal peripheral, each SW component can directly access RCC registers to control reset and clock gating.
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment | |||||
---|---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
Power & Thermal | RCC | RCC | ☐ | ☐ | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the RCC instance.
Feature | Runtime allocation | Comment | ||||
---|---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | ||
FCALC | ☑OP-TEE | ⬚ | ☐ | ⬚ | ||
SYSRST | ✓OP-TEE ✓TF-A BL31 |
⬚ | ||||
BOOT_STDB | ✓OP-TEE ✓TF-A BL31 |
⬚ | ||||
RDCR | ✓OP-TEE ✓TF-A BL31 |
⬚ | ||||
SYSCLK | ✓OP-TEE ✓TF-A BL31 |
⬚ | ||||
CPU1_RES | ✓OP-TEE ✓TF-A BL31 |
⬚ | ||||
CPU2_RES | ☐ if TZ_EN | ☐ if TZ_DIS | ||||
CPU3_RES | ☐OP-TEE | ☐ | ☐ | ☐ | ||
DEBUG_CFGR | ☑OP-TEE | ☐ | ☐ | ☐ | ||
SYSRAM_CFGR | ☑OP-TEE ☑TF-A BL31 |
|||||
VDERAM_CFGR | ☐OP-TEE | ☐ | ⬚ | ☐ | ||
RETRAM_CFGR | ☐OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
BKPSRAM_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
SRAM1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
SRAM2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
LPSRAM1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
LPSRAM2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
LPSRAM3_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
HPDMA1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
HPDMA2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
HPDMA3_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
LPDMA_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
IPCC1_CFGR | ☑OP-TEE | ☐ | ☐ | ☐ | ||
IPCC2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
HSEM_CFGR | ☑OP-TEE | ☐ | ⬚ | ☐ | ||
GPIOA_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOB_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOC_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOD_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOE_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOF_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOG_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOH_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOI_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOJ_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOK_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
GPIOZ_CFGR | ☑OP-TEE ☑TF-A BL31 |
☐ | ☐ | ☐ | ||
RTC_CFGR | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ | ||
BSEC_CFGR | ☑OP-TEE ☑TF-A BL31 |
|||||
DDRC_CFGR | ☑OP-TEE ☑TF-A BL31 |
|||||
PLL3_CFGR | ☑OP-TEE | ⬚ | ☐ | ⬚ | ||
SYSCPU1_CFGR | ✓OP-TEE ✓TF-A BL31 |
|||||
MCO1_CFGR | ☐OP-TEE | ⬚ | ☐ | ⬚ | ||
MCO2_CFGR | ☐OP-TEE | ⬚ | ☐ | ⬚ | ||
OSPI1_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
OSPI2_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
FMC_CFGR | ☐OP-TEE | ☐ | ☐ | ☐ | ||
HSI_MON | ☑OP-TEE | ☐ | ☐ | ☐ |
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers managing the RCC peripheral for the embedded software components listed in the above tables.
- Linux®: Reset framework and Clock framework
- OP-TEE: drivers in core/drivers/clk/
- TF-A: drivers in drivers/st/clk/
- U-Boot: drivers in drivers/clk/stm32/
- STM32Cube: HAL RCC drivers
- stm32mp1xx_hal_rcc.c
- Unsupported domain!
See also the SCMI overview.
5. How to assign and configure the peripheral[edit | edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
For configuration of reset part of RCC, refer to Reset device tree configuration.
For configuration of clock part of RCC, the STM32CubeMX tool allows configuring the clock tree and integrates all the information documented in the STM32 MPU reference manuals. It is highly recommended to use it to generate your device tree as explained in:
On STM32MP15x lines , the RCC security level differs for each boards and is defined by RCC compatible in OP-TEE device tree:
- "st,stm32mp1-rcc-secure": sets TZEN to 1 and MCKPROT to 0
- "st,stm32mp1-rcc": sets TZEN to 0 and MCKPROT to 0
The STMicroelectronics STM32MP15x lines boards use TZEN=1.
6. How to go further[edit | edit source]
The RCC is interfaced with the HDP internal peripheral, thus offering the flexibility to monitor the main RCC state signals on the debug pins.
Please refer to the STM32MPU reference manuals for the full list of signals that can be monitored.
7. References[edit | edit source]