USBPHYC internal peripheral: Difference between revisions

Latest revision as of 07:24, 24 October 2024↑

Applicable for

1. Article purpose[edit | edit source]↑

The purpose of this article is to:

briefly introduce the USBPHYC peripheral and its main features,
indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
list the software frameworks and drivers managing the peripheral,
explain how to configure the peripheral.

2. Peripheral overview[edit | edit source]↑

The USBPHYC peripheral is a block that contains a dual port USB high-speed UTMI+ PHY and a UTMI switch. It makes the interface between:

the internal USB controllers (USBH and OTG)
the external USB physical lines (DP, DM)

The USBPHYC peripheral:

controls a two port high-speed PHY:
- Port1 connected to the USBH controller
- Port2 connected via the UTMI+switch to the USBH or to the OTG controller
sets the PLL values
performs other controls (and monitoring) on the PHY.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage[edit | edit source]↑

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm^® Cortex^®-A processor(s), and the STM32CubeMPU Package running on the Arm^® Cortex^®-M processor.

3.1. Boot time assignment[edit | edit source]↑

3.1.1. On STM32MP1 series[edit | edit source]↑

USBPHYC instances are boot devices that support Flash programming with STM32CubeProgrammer.

The USBPHYC peripheral is used by ROM code, FSBL and SSBL when using OTG in Device mode (DFU).

Click on to expand or collapse the legend...

Domain	Peripheral	Boot time allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 non-secure (U-Boot)	Comment
High speed interface	USBPHYC (USB HS PHY controller)	USBPHYC (USB HS PHY controller)	✓	☐	☐	The USBPHYC can be used by ROM code, FSBL and SSBL in DFU mode to support serial boot. It can be used also in U-boot by OTG and USBH with command line tools.

3.2. Runtime assignment[edit | edit source]↑

3.2.1. On STM32MP13x lines [edit | edit source]↑

Click on to expand or collapse the legend...

Domain	Peripheral	Runtime allocation			Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Comment
High speed interface	USBPHYC (USB HS PHY controller)	USBPHYC (USB HS PHY controller)	⬚	☐	Assignment (single choice)

3.2.2. On STM32MP15x lines [edit | edit source]↑

Click on to expand or collapse the legend...

Domain	Peripheral	Runtime allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
High speed interface	USBPHYC (USB HS PHY controller)	USBPHYC (USB HS PHY controller)		☐	⬚

4. Software frameworks and drivers[edit | edit source]↑

Below are listed the software frameworks and drivers managing the USBPHYC peripheral for the embedded software components listed in the above tables.

Linux^®: PHY framework
U-Boot: PHY uclass (drivers/phy/phy-uclass.c ) and driver (drivers/phy/phy-stm32-usbphyc.c )

5. How to assign and configure the peripheral[edit | edit source]↑

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

For U-boot and Linux kernel configuration, please refer to USBPHYC device tree configuration.

@@ Line 1: / Line 1: @@
+{{ApplicableFor
+|MPUs list=STM32MP13x, STM32MP15x
+|MPUs checklist=STM32MP13x, STM32MP15x, STM32MP21x, STM32MP23x, STM32MP25x
+}}
+<noinclude></noinclude>
 ==Article purpose==
-The purpose of this article is to
+The purpose of this article is to:
-* briefly introduce the USBPHYC  peripheral and its main features
+* briefly introduce the USBPHYC peripheral and its main features,
-* indicate the level of security supported by this hardware block
+* indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
-* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
+* list the software frameworks and drivers managing the peripheral,
-* explain, when necessary, how to configure the USBPHYC peripheral.
+* explain how to configure the peripheral.
 ==Peripheral overview==
-The '''USBPHYC''' peripheral is a block that contains a dual port USB high-speed UTMI+ PHY and a UTMI switch. It makes the interface between:
+The '''USBPHYC ''' peripheral is a block that contains a dual port USB high-speed UTMI+ PHY and a UTMI switch. It makes the interface between:
 * the internal USB controllers ([[USBH_internal_peripheral|USBH]] and [[OTG_internal_peripheral|OTG]])
 * the external USB physical lines (DP, DM)
-===Features===
+The USBPHYC peripheral:
-The '''USBPHYC''' peripheral:
 * controls a two port high-speed PHY:
 ** Port1 connected to the [[USBH_internal_peripheral|USBH]] controller
@@ Line 21: / Line 26: @@
 [[File:USBPHYC.png|link=]]
-Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.
+Refer to the [[STM32 MPU resources#Reference manuals|STM32 MPU reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
-===Security support===
+==Peripheral usage==
-The '''USBPHYC''' is a '''non-secure''' peripheral.
+This chapter is applicable in the scope of the '''OpenSTLinux BSP''' running on the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A processor(s), and the '''STM32CubeMPU Package''' running on the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M processor.
-==Peripheral usage and associated software==
+===Boot time assignment===
-===Boot time===
+====On {{MicroprocessorDevice | device=1}}====
 USBPHYC instances are boot devices that support Flash programming with [[STM32CubeProgrammer]].
-The USBPHYC peripheral is used by [[STM32MP15 ROM code overview|ROM code]], [[Boot chains overview|FSBL]] and [[Boot chains overview|SSBL]] when using [[OTG_internal_peripheral|OTG]] in Device mode (DFU).<br>
+The USBPHYC peripheral is used by [[STM32 MPU ROM code overview|ROM code]], [[Boot chain overview|FSBL]] and [[Boot chain overview|SSBL]] when using [[OTG_internal_peripheral|OTG]] in Device mode (DFU).<br>
-The [[Boot chains overview|SSBL]] can use [[OTG_internal_peripheral|OTG]] in Host mode or [[USBH_internal_peripheral|USBH]] (mass storage). The USBPHYC peripheral can be used to boot on a kernel stored on a USB key, or after a kernel panic to perform the crash dump saving to the USB key.
+{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}}
+<section begin=stm32mp13_boottime /><section begin=stm32mp15_boottime />
+| rowspan="1" | High speed interface
+| rowspan="1" | [[USBPHYC internal peripheral|USBPHYC (USB HS PHY controller)]]
+| USBPHYC (USB HS PHY controller)
+| <span title="system peripheral" style="font-size:21px">✓</span>
+| <span title="assignable peripheral" style="font-size:21px">☐</span>
+| <span title="assignable peripheral" style="font-size:21px">☐</span>
+| The USBPHYC can be used by [[STM32 MPU ROM code overview|ROM code]], [[Boot chain overview|FSBL]] and [[Boot chain overview|SSBL]] in DFU mode to support serial boot.</br> It can be used also in U-boot by [[OTG_internal_peripheral|OTG]] and [[USBH_internal_peripheral|USBH]] with command line tools.
+|-
+<section end=stm32mp13_boottime /><section end=stm32mp15_boottime />
+|}
-===Runtime===
+===Runtime assignment===
-====Overview====
+====On {{MicroprocessorDevice | device=13}}====
-The USBPHYC peripheral can be allocated to the the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be used under Linux<sup>&reg;</sup> with [[PHY overview | PHY framework]].
+{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp13_runtime}}
+<section begin=stm32mp13_runtime />
+| rowspan="1" | High speed interface
+| rowspan="1" | [[USBPHYC internal peripheral|USBPHYC (USB HS PHY controller)]]
+| USBPHYC (USB HS PHY controller)
+| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
+| <span title="assignable peripheral" style="font-size:21px">☐</span>
+| Assignment (single choice)
+|-
+<section end=stm32mp13_runtime />
+|}
-The [[#Peripheral assignment|peripheral assignment]] chapter describes which peripheral instance can be assigned to which context.
+====On {{MicroprocessorDevice | device=15}}====
+{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp15_runtime}}
+<section begin=stm32mp15_runtime />
+| rowspan="1" | High speed interface
+| rowspan="1" | [[USBPHYC internal peripheral|USBPHYC (USB HS PHY controller)]]
+| USBPHYC (USB HS PHY controller)
+|
+| <span title="assignable peripheral" style="font-size:21px">☐</span>
+| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
+|
+|-
+<section end=stm32mp15_runtime />
+|}
-====Software frameworks====
+==Software frameworks and drivers==
-{{:Internal_peripherals_software_table_template}}
+Below are listed the software frameworks and drivers managing the USBPHYC peripheral for the embedded software components listed in the above tables.
- | High-speed interface
- | [[USBPHYC internal peripheral|USBPHYC (USB HS PHY controller)]]
- |
- | [[PHY overview|Linux PHY framework]]
- |
- |
- |-
- |}
-====Peripheral configuration====
+* '''Linux<sup>&reg;</sup>''': [[PHY overview | PHY framework]]
-The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals) according to the information given in the corresponding software framework article.
+* '''U-Boot''': PHY uclass ({{CodeSource | U-Boot | drivers/phy/phy-uclass.c}}) and driver ({{CodeSource | U-Boot | drivers/phy/phy-stm32-usbphyc.c}})
-For Linux kernel configuration, please refer to [[USBPHYC device tree configuration|USBPHYC device tree configuration]].
+==How to assign and configure the peripheral==
+The peripheral assignment can be done via the [[STM32CubeMX]] graphical tool (and manually completed if needed).<br />
+This tool also helps to configure the peripheral:
+* partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
+* HAL initialization code generation for the STM32CubeMPU Package.
+The configuration is applied by the firmware running in the context in which the peripheral is assigned.
-====Peripheral assignment====
+For U-boot and Linux kernel configuration, please refer to [[USBPHYC device tree configuration|USBPHYC device tree configuration]].
-{{:Internal_peripherals_assignment_table_template}}
-<onlyinclude>
- | rowspan="1" | High speed interface
- | rowspan="1" | [[USBPHYC internal peripheral|USBPHYC (USB HS PHY controller)]]
- | USBPHYC (USB HS PHY controller)
- |
- | <span title="assignable peripheral" style="font-size:21px">☐</span>
- |
- |
- |-
-</onlyinclude>
- |}
 <noinclude>
 [[Category:High speed interface peripherals]]
+{{ArticleBasedOnModel | Internal peripheral article model}}
 {{PublicationRequestId | 10276 | 2019-01-14 | AnneJ}}
-{{ArticleBasedOnModel | Internal peripheral article model}}
 </noinclude>