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Approved version. Approved on: 12:04, 30 May 2022

Last edited one week ago

STM32MP13 OTP mapping

Applicable for

STM32MP13x lines

1. Memory mapping[edit | edit source]↑

The table below gives an overview of the BSEC OTP memory mapping with useful information in the context of this Wiki reading.
OTP words 0 to 31 are called lower OTP and words 32 to 95 are called upper OTP.
Further information for the words and fields that are not explicitly described here can be found in the reference manual.

OTP word

Bit field (size)

Name

Description

0

31-7 (25 bits)

reserved

5, 3 (2 bits)

is closed

Warning

These 'is_closed' bits must never be programmed to 1 on product without secure boot option available: this is indicated in the security field of the chip part number.

6, 4, 2-0 (5 bits)

reserved

1-2

-

-

See the reference manual

3

31-30 (2 bits)

HSE value

29-27 (3 bits)

primary boot source

26-24 (3 bits)

secondary boot source

23-16 (8 bits)

boot source disable

If different from zero each bit disables a boot source

15 (1 bit)

data cache disabling

14-7 (8 bits)

UART instances disabling

If different from zero then each bit disables an UART instance

6 (1 bit)

USB DP pullup disabling

5 (1 bit)

PLL disabling

4-3 (2 bits)

SD card memory interface

2-1 (2 bits)

e•MMC™ memory interface

0 (1 bit)

QSPI non default AFmux

4

31-0 (32 bits)

monotonic counter

This is an anti rollback monotonic counter : on closed devices, the ROM code checks that it is less or equal to the one stored in the loaded image header.

5-7

31-28 (4 bits)

AFmux configuration - port1[3:0]

Bank id

27-24 (4 bits)

AFmux configuration - pin1[3:0]

Pin id

23-20 (4 bits)

AFmux configuration - afmux1[3:0]

AFmux value

19-16 (4 bits)

AFmux configuration - mode1[3:0]

Pin mode

15-12 (4 bits)

AFmux configuration - port0[3:0]

Bank id

11-8 (4 bits)

AFmux configuration - pin0[3:0]

Pin id

7-4 (4 bits)

AFmux configuration - afmux0[3:0]

AFmux value

3-0 (4 bits)

AFmux configuration - mode0[3:0]

Pin mode

8

31-0 (32 bits)

reserved

9

31 (1 bit)

nand param stored in otp

FMC NAND parameters storage flag

Notes:

serial NAND parameters must always be stored in OTP. This bit is useless for serial NAND.
there are two NAND parameters banks. The value of NAND configuration distribution determines the bank to be used.

30-29 (2 bits)

nand page size[1:0]

FMC or serial NAND page size

Note: this parameter is part of NAND parameters bank1.

28-27 (2 bits)

nand block size[1:0]

FMC or serial NAND block size

Note: this parameter is part of NAND parameters bank1.

26-19 (8 bits)

nand block nb[7:0]

FMC or serial NAND number of blocks in unit of 256 blocks (nb blocks = N * 256)

18 (1 bit)

fmc nand width

FMC NAND width

Note: this parameter is part of NAND parameters bank1.

17-15 (3 bits)

fmc ecc bit nb[2:0]

FMC NAND number of ECC bits

Note: this parameter is part of NAND parameters bank1.

14 (1 bit)

spinand needs plane select

Serial NAND needs plane select

Note: this parameter is part of NAND parameters bank1.

13-8 (6 bits)

reserved

7 (1 bit)

FSBL decryption priority

6 (1 bit)

SSP success

5 (1 bit)

SSP request

4 (1 bit)

eMMC 128KB boot partition support

3 (1 bit)

disable ddr power optim

Disable DDR PLL switch off sequence

2 (1 bit)

disable HSE bypass detection

1 (1 bit)

disable HSE frequency autodetection

0 (1 bit)

disable ROM code traces

10

31-18 (14 bits)

reserved

17-16 (2 bits)

nand page size[1:0]

NAND parameters bank2 : FMC or serial NAND page size

15-14 (2 bits)

nand block size[1:0]

NAND parameters bank2 : FMC or serial NAND block size

13-6 (8 bits)

nand block nb[7:0]

NAND parameters bank2 : FMC or serial NAND number of blocks in unit of 256 blocks (nb blocks = N * 256)

5 (1 bit)

fmc nand width

NAND parameters bank2 : FMC NAND width

4-2 (3 bits)

fmc ecc bit nb[2:0]

NAND parameters bank2 : FMC NAND number of ECC bits

1 (1 bit)

spinand needs plane select

NAND parameters bank2 : serial NAND needs plane select

0 (1 bit)

NAND configuration distribution

Distribution of NAND parameters bank1 and bank2.

11-21

-

-

See the reference manual

22

31-8 (24 bits)

reserved

7-0 (8 bits)

signing key id monotonic counter

This is an key revocation monotonic counter used by the ROM to checks that it is less or equal to the active signing key id stored in the loaded image header.

23

-

-

See the reference manual

24

31-0 (32 bits)

PKHTH[31:0]

The Public Key Hashes Table Hash (PKHTH) is the SHA256 hash of the 8 SHA256 hashes of the 8 ECDSA public keys usable for the Secure boot

25

31-0 (32 bits)

PKHTH[63:32]

26

31-0 (32 bits)

PKHTH[95:64]

27

31-0 (32 bits)

PKHTH[128:96]

28

31-0 (32 bits)

PKHTH[159:128]

29

31-0 (32 bits)

PKHTH[191:160]

30

31-0 (32 bits)

PKHTH[223:192]

31

31-0 (32 bits)

PKHTH[255:224]

32-55

-

-

See the reference manual

56

31-0 (32 bits)

rma unlock passwd

Password required for RMA unlock request

57

31-0

mac1[47:16]

ETH MAC addresses for STMicroelectronics boards

58

15-0

mac1[15:0]

31-16

mac2[47:32]

59

31-0

mac2[31:0]

60-91

-

-

See the reference manual

92

31-0 (32 bits)

EDMK[31:0]

The Encryption Decryption Master Key (EDMK) is used in combination with the derivation constant stored in the header file to derive the FSBL decryption key.

93

31-0 (32 bits)

EDMK[63:32]

94

31-0 (32 bits)

EDMK[95:64]

95

31-0 (32 bits)

EDMK[128:96]

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