STM32MP23 peripherals overview

Applicable for

This article lists all internal peripherals embedded in STM32MP23x lines and shows the assignment possibilities to the execution contexts for each one of them.
From this article, you can also access to individual peripheral articles with information related to the overview and configuration aspects.

1. Internal peripherals overview[edit | edit source]

The figure below shows all peripherals embedded in STM32MP23x lines , grouped per functional domains that are reused in many places of this wiki to structure the articles.
Several execution contexts exist on STM32MP23x lines ^[1], corresponding to the different Arm cores and associated security modes:

Arm dual core Cortex-A35 secure (Trustzone), running ROM code and TF-A BL2 at boot time, and running OP-TEE and/or TF-A BL31 at runtime
Arm dual core Cortex-A35 non secure , running U-Boot at boot time, and running Linux at runtime
Arm Cortex-M33 secure (Trustzone), running TF-M
Arm Cortex-M33 non-secure , running STM32Cube

The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

When a peripheral box owns execution context color, that means the assignment of this peripheral is fixed by hardware to the execution context.
When a peripheral box owns a mix of two execution colors that means this peripheral is shared by hardware between the two execution contexts.
When a peripheral box has dark gray color, that means this peripheral is protected by RIF and could be assigned to any execution context.
When a peripheral box has light gray color, that means this peripheral is a RIF-aware peripheral. This peripheral owns several features which can be assigned independently to any execution context.

Internal peripheral assignment tables list assignment capabilities for each peripheral.

Both the diagram below and the following summary tables (in Internal peripherals runtime assignment and Internal peripherals boot time assignment chapters below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP23 reference manual ^[2] may expose more possibilities than what is shown here.

STM32MP23 internal peripherals overview

2. Internal peripherals runtime assignment[edit | edit source]

Click on to expand or collapse the legend...

STM32MP23 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
☐ means that the peripheral can be assigned to the given runtime context.
☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP23 reference manuals.

ADF internal peripheral

Domain	Peripheral	Runtime allocation					Comment
Domain	Peripheral	Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)	Comment
Core/Processors	Arm^® Cortex^®-A35	Arm^® Cortex^®-A35	✓^OP-TEE ✓^{TF-A BL31}	✓
Core/Processors	Arm^® Cortex^®-M33 (coprocessor)	Arm^® Cortex^®-M33 (coprocessor)	☐^OP-TEE	☐	☐	✓	Controlled by LInux or OP-TEE. Running the STM32CubeMP2 firmware.
Power & Thermal	VREFBUF	VREFBUF	☑^OP-TEE	⬚	⬚	⬚	OP-TEE offers SCMI regulator service to manage VREFBUF
Analog	ADC	ADC12	☐^OP-TEE	☐	⬚	☐
Analog	ADC	ADC3	☐^OP-TEE	☐	⬚	☑	ADC3 may be used by the UCSI firmware to measure the Vbus level on the Type-C connector.
Analog	MDF	MDF1	⬚^OP-TEE	☐	⬚	☐
Low speed interface or audio	SPI	SPI2S1	⬚^OP-TEE	☐	⬚	☐
		SPI2S2	⬚^OP-TEE	☐	⬚	☐
		SPI2S3	⬚^OP-TEE	☐	⬚	☐
		SPI4	⬚^OP-TEE	☐	⬚	☐
		SPI5	⬚^OP-TEE	☐	⬚	☐
		SPI8	⬚^OP-TEE	☐	⬚	☐
Audio	SPDIFRX	SPDIFRX	⬚^OP-TEE	☐	⬚	☐
Audio	SAI	SAI1	⬚^OP-TEE	☐	⬚	☐
		SAI2	⬚^OP-TEE	☐	⬚	☐
		SAI3	⬚^OP-TEE	☐	⬚	☐
		SAI4	⬚^OP-TEE	☐	⬚	☐
Coprocessor	IPCC	IPCC1	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core	SYSCFG	SYSCFG	☑	☑	☑	☑
Core	STGEN	STGEN	☑^OP-TEE ☑^{TF-A BL31}	Read-only ^(STGENR)	Read-only ^(STGENR)	Read-only ^(STGENR)
Core	RTC	RTC	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/DMA	HPDMA	HPDMAx (x = 1 to 3)	☐^OP-TEE	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/Interrupts	EXTI	EXTI1	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/Interrupts	EXTI	EXTI2	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/Interrupts	NVIC	NVIC CM33			✓	✓	Fixed to CM33
Core/Interrupts	GIC	GIC	✓^OP-TEE ✓^{TF-A BL31}	✓			Fixed to CA35
Core/IOs	GPIO	GPIO	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/RAM	SYSRAM	SYSRAM	☑^BL31 ☐^OP-TEE	☑	☐	☐	Cortex-A35 secure section required for low power entry and exit
Core/RAM	DDRCTRL	DDR	✓^OP-TEE ✓^{TF-A BL31}	⬚	☐	⬚
Core/RAM	BKPSRAM	BKPSRAM	⬚^OP-TEE ☑^{TF-A BL31}	⬚	☑	⬚	TF-M uses BKPSRAM for ITS (Internal Trusted Storage)
Core/RAM	RETRAM	RETRAM	☐^OP-TEE ☐^{TF-A BL31}	⬚	☑	☐
Core/RAM	SRAM	SRAM1	☑^OP-TEE ☐^BL31	☐	☐	☐	OP-TEE populate OTP shadow region
Core/RAM	SRAM	SRAM2	☐^OP-TEE ☐^BL31	☐	☐	☐
Core/Timers	TIM	TIM1	⬚^OP-TEE	☐	⬚	☐
		TIM10	⬚^OP-TEE	☐	⬚	☐
		TIM11	⬚^OP-TEE	☐	⬚	☐
		TIM12	⬚^OP-TEE	☐	⬚	☐
		TIM13	⬚^OP-TEE	☐	⬚	☐
		TIM14	⬚^OP-TEE	☐	⬚	☐
		TIM15	⬚^OP-TEE	☐	⬚	☐
		TIM16	⬚^OP-TEE	☐	⬚	☐
		TIM17	⬚^OP-TEE	☐	⬚	☐
		TIM2	⬚^OP-TEE	☐	⬚	☐
		TIM3	⬚^OP-TEE	☐	⬚	☐
		TIM4	⬚^OP-TEE	☐	⬚	☐
		TIM5	⬚^OP-TEE	☐	⬚	☐
		TIM6	⬚^OP-TEE	☐	⬚	☐
		TIM7	⬚^OP-TEE	☐	⬚	☐
		TIM8	⬚^OP-TEE	☐	⬚	☐
Core/Timers	LPTIM	LPTIM1	☐^OP-TEE	☐	⬚	☐	LPTIM1 can be used for HSE monitoring.
		LPTIM2	☐^OP-TEE	☐	⬚	☐
		LPTIM3	☐^OP-TEE	☐	⬚	☐	LPTIMy (y = 3, 4, 5) can be used for scheduling in low power modes by Linux
		LPTIM4	☐^OP-TEE	☐	⬚	☐	LPTIMy (y = 3, 4, 5) can be used for scheduling in low power modes by Linux
		LPTIM5	☐^OP-TEE	☐	⬚	☐	LPTIMy (y = 3, 4, 5) can be used for scheduling in low power modes by Linux
Core/Watchdog	IWDG	IWDG1	☑^OP-TEE ☑^{TF-A BL31}	☐
		IWDG2	☐^OP-TEE ☐^{TF-A BL31}	☐
		IWDG3			☑	☐
		IWDG4			☐	☑
Core/Watchdog	WWDG	WWDG1			⬚	☐
High speed interface	USB3DR	USB3DR	⬚^OP-TEE	☐	⬚	⬚	The USB3DR running at USB2 speed.
High speed interface	USBH	USBH	⬚^OP-TEE	☐	⬚	⬚
High speed interface	UCPD	UCPD1	⬚^OP-TEE	⬚	⬚	☐
High speed interface	USB2PHY	USB2PHY1	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐	Allocation inherited from USBH
High speed interface	USB2PHY	USB2PHY2	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐	Allocation inherited from USB3DR
Low speed interface	USART	USART1	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART2	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART3	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART4	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART5	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART6	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART7	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
Low speed interface	I2C	I2C1	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C2	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C7	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C8	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
Low speed interface	I3C	I3C1	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐
		I3C2	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐
		I3C4	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐
Mass storage	OCTOSPI	OCTOSPI1	⬚^OP-TEE	☐	☐	☐	OP-TEE need to access OCTOSPI1 at boot time to set OSPIM mode
Mass storage	OCTOSPI	OCTOSPI2	⬚^OP-TEE	☐	☐	☐	OP-TEE need to access OCTOSPI2 at boot time to set OSPIM mode
Mass storage	OCTOSPIM	OCTOSPIM	☐^OP-TEE	☐	☐	☐
Mass storage	FMC	FMC	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Mass storage	SDMMC	SDMMC1	⬚^OP-TEE	☐	☐	☐
		SDMMC2	⬚^OP-TEE	☐	☐	☐
		SDMMC3	⬚^OP-TEE	☐	☐	☐
Networking	FDCAN	FDCAN1	⬚^OP-TEE	☐	⬚	☐
Networking	FDCAN	FDCAN2	⬚^OP-TEE	☐	⬚	☐
Power & Thermal	RCC	RCC	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Power & Thermal	PWR	PWR	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Power & Thermal	DTS	DTS	⬚^OP-TEE	☐		⬚
Security	BSEC	BSEC	✓^OP-TEE ✓^{TF-A BL31}
Security	RNG	RNG	☑^OP-TEE	⬚	☐	⬚
Security	HASH	HASH	☐^OP-TEE	☐	☐	☐
Security	CRYP	CRYP1	☐^OP-TEE	☐	⬚	☐
Security	CRYP	CRYP2	☐^OP-TEE	☐	⬚	☐
Security	CRC	CRC	⬚^OP-TEE	☐	⬚	☐
Security	SAES	SAES	☐^OP-TEE	⬚	☐	⬚
Security	TAMP	TAMP	☑	⬚	⬚	⬚	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Security	OTFDEC	OTFDEC1	⬚^OP-TEE	⬚	⬚	⬚
Security	OTFDEC	OTFDEC2	⬚^OP-TEE	⬚	⬚	⬚
Security	PKA	PKA	☑^OP-TEE	⬚	☐	⬚
Security	RIFSC	RIFSC	☑^OP-TEE	☑	☑	☐
Security	RISAB	RISAB1	☑^OP-TEE	⬚	☐	⬚
		RISAB2	☑^OP-TEE	⬚	☐	⬚
		RISAB3	☑^OP-TEE	⬚	☐	⬚
		RISAB4	☑^OP-TEE	⬚	☐	⬚
		RISAB5	☑^OP-TEE	⬚	☐	⬚
		RISAB6	☑^OP-TEE	⬚	☐	⬚
Security	RISAF	RISAF1	☑^OP-TEE	⬚	☐	⬚	OP-TEE configures all regions
		RISAF2	☑^OP-TEE	⬚	☐	⬚	OP-TEE configures all regions
		RISAF4	☑^OP-TEE	⬚	☐	⬚	OP-TEE configures all regions except its own
Security	IAC	IAC	✓^OP-TEE				Fixed to TDCID
Trace & debug	SERC	SERC	☑^OP-TEE	⬚
Trace & Debug	HDP	HDP	⬚^OP-TEE	☑	⬚	⬚
Trace & Debug	DDRPERFM	DDRPERFM	⬚^OP-TEE	☐	⬚	⬚	Part of DDRSS protected by RCC DDR_CFGR
Visual	GPU	GPU	⬚^OP-TEE	☑	⬚	⬚
Visual	DSI	DSI	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Visual	LTDC	LTDC	☐^OP-TEE	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Visual	DCMI	DCMI	⬚^OP-TEE	☑	⬚	☐
Visual	CSI	CSI	⬚^OP-TEE	☑	⬚	☐
Visual	LVDS	LVDS	⬚^OP-TEE	☑	⬚	☐
Visual	DCMIPP	DCMIPP	⬚^OP-TEE	☑	⬚	☐
Visual	VDEC	VDEC	⬚^OP-TEE	☑	⬚	⬚

3. Internal peripherals boot time assignment[edit | edit source]

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
☐ means that the peripheral can be assigned to the given boot time context.
☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

ADF internal peripheral

Domain	Peripheral	Boot time allocation				Comment
Domain	Peripheral	Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)	Comment
Core/Processors	Arm^® Cortex^®-A35	Arm^® Cortex^®-A35	✓	✓	✓
Core/Processors	Arm^® Cortex^®-M33 (coprocessor)	Arm^® Cortex^®-M33 (coprocessor)		⬚	☐	How to start the coprocessor from the bootloader How_to_protect_the_coprocessor_firmware
Analog	VREFBUF	VREFBUF			⬚	OP-TEE offers SCMI regulator service to manage VREFBUF
Analog	ADC	ADC12		⬚	☐
Analog	ADC	ADC3		⬚	☐
Analog	MDF	MDF1			⬚
Low speed interface or audio	SPI	SPI2S1		⬚	☐
		SPI2S2		⬚	☐
		SPI2S3		⬚	☐
		SPI4		⬚	☐
		SPI5		⬚	☐
		SPI8		⬚	☐
Audio	SPDIFRX	SPDIFRX			⬚
Audio	SAI	SAI1			⬚
		SAI2			⬚
		SAI3			⬚
		SAI4			⬚
Coprocessor	IPCC	IPCC1	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core	STGEN	STGEN	✓	☑	Read-only ^(STGENR)
Core	RTC	RTC	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/DMA	HPDMA	HPDMAx (x = 1 to 3)	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/Interrupts	EXTI	EXTI1	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/Interrupts	EXTI	EXTI2	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/Interrupts	GIC	GIC		⬚	⬚
Core/IOs	GPIO	GPIO	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/RAM	SYSRAM	SYSRAM	✓	✓
Core/RAM	DDRCTRL	DDR		✓	⬚
Core/RAM	BKPSRAM	BKPSRAM		☑	⬚
Core/RAM	RETRAM	RETRAM		☑		DDR parameters are stored in RETRAM by TF-A BL2.
Core/RAM	SRAM	SRAM1	✓	✓	☐	Used during cold boot by TF-A BL2 for DDR firmware loading
Core/RAM	SRAM	SRAM2		☐	☐
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17)		⬚	⬚
Core/Timers	LPTIM	LPTIMx (x = 1 to 5)		⬚	⬚
Core/Watchdog	IWDG	IWDG1	✓	☑	☐
		IWDG2	✓	☐	☐
		IWDG3
		IWDG4
Core/Watchdog	WWDG	WWDG1
High speed interface	USB3DR	USB3DR	☐	☐	☐	The USB3DR can be used by ROM code, FSBL and SSBL in DFU mode to support serial boot. It can be used also in U-boot with command line tools.
High speed interface	USBH	USBH		⬚	☐
High speed interface	UCPD	UCPD1		⬚	⬚
High speed interface	USB2PHY	USB2PHY1	⬚	⬚	☐	USB2PHY1 can be used in U-boot by USBH with command line tools.
High speed interface	USB2PHY	USB2PHY2	☐	☐	☐	USB2PHY2 can be used by ROM code, FSBL and SSBL in DFU mode to support serial boot. It can be used also in U-boot by USB3DR with command line tools.
Low speed interface	USART	USART1	☐	☐	☐
		USART2	☐	☐	☐
		USART3	☐	☐	☐
		UART4	☐	☐	☐
		UART5	☐	☐	☐
		USART6	☐	☐	☐
		UART7	☐	☐	☐
Low speed interface	I2C	I2C1		☐	☐
		I2C2		☐	☐
		I2C7		☐	☐
		I2C8		☐	☐
Low speed interface	I3C	I3C1		⬚	☐
		I3C2		⬚	☐
		I3C4		⬚	☐
Mass storage	OCTOSPI	OCTOSPI1	☐	☐	☐
Mass storage	OCTOSPI	OCTOSPI2		☐	☐
Mass storage	OCTOSPIM	OCTOSPIM	☐	☐	☐	TF-A BL2 relies on OCTOSPIM configuration applied by ROM code
Mass storage	FMC	FMC	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Mass storage	SDMMC	SDMMC1	☐	☐	☐
		SDMMC2	☐	☐	☐
		SDMMC3			☐
Networking	FDCAN	FDCAN1			⬚
Networking	FDCAN	FDCAN2			⬚
Power & Thermal	RCC	RCC	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Power & Thermal	PWR	PWR	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Power & Thermal	DTS	DTS			⬚
Security	BSEC	BSEC	✓	✓
Security	RNG	RNG	✓	☑	⬚
Security	HASH	HASH	✓	☑	☐
Security	CRYP	CRYP1	☑	⬚	⬚	ROM code allocation is managed with the bit 8 in OTP 16
Security	CRYP	CRYP2			⬚
Security	SAES	SAES	☐	☑	⬚	ROM code allocation is managed with the bit 8 in OTP 16
Security	TAMP	TAMP	✓	☑	☑	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Security	OTFDEC	OTFDEC1		⬚	⬚
Security	OTFDEC	OTFDEC2		⬚	⬚
Security	PKA	PKA	✓	☑	⬚	Assignment is mandatory only for secure boot
Security	RIFSC	RIFSC	✓	☑	☑
Security	RISAF	RISAF1		☐	⬚
		RISAF2		☐	⬚
		RISAF4		☑	⬚	FSBL TF-A configures Cortex-A secure and encrypted memory regions
Security	IAC	IAC		⬚		Fixed to TDCID
Trace & debug	SERC	SERC		⬚
Trace & Debug	DBGMCU	DBGMCU	⬚	⬚	⬚
Trace & Debug	HDP	HDP		⬚	⬚
Trace & Debug	DDRPERFM	DDRPERFM		⬚	⬚
Visual	GPU	GPU			⬚
Visual	DSI	DSI	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Visual	LTDC	LTDC	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Visual	DCMI	DCMI			⬚
Visual	CSI	CSI			⬚
Visual	LVDS	LVDS			☑
Visual	DCMIPP	DCMIPP			⬚
Visual	VDEC	VDEC			⬚

4. References[edit | edit source]

[1] STM32 MPU microprocessor devices: multiple-core architecture concepts

[2] STM32MP23 reference manuals

[1]

[2]