STM32MP2 SRAM internal memory

Applicable for

STM32MP21x lines, STM32MP23x lines, STM32MP25x lines

---

1. Article purpose

The purpose of this article is to:

• briefly introduce the SRAM internal memory peripheral and its main features,
• indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
• list the software frameworks and drivers managing the peripheral,
• explain how to configure the peripheral.

2. Peripheral overview

On STM32MP21x lines :

• The SRAM peripheral is 64-Kbyte wide and physically near to the Cortex-M33 for optimized performances from this core. The 64BK fits in only one bank: the SRAM1.

On STM32MP23x lines  and STM32MP25x lines :

• The SRAM peripheral is 256-Kbyte wide and physically near to the Cortex-M33 for optimized performances from this core.
• It is split into two separate banks:
  • SRAM1 (128 Kbytes)
  • SRAM2 (128 Kbytes)

Each bank is protected via a RISAB memory firewall allowing to define 4-Kbyte granularity regions with different access rights. Each region could be assigned to different execution contexts. Each bank also owns automatic clock gating (for power management optimization) which can be linked:

• either on one processor low power state if the bank is only assigned to this processor,
• or on system low power state if the bank is assigned to several processors.

Banks content is preserved in (LPLV)Stop1/2 low power mode but it is lost in Standby low power mode as not supplied.
Moreover, SRAM1 is protected by tamper detection circuit and is erased by hardware in case of tamper detection.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm Cortex-A processor(s), and the STM32CubeMPU Package running on the Arm Cortex-M processor.

3.1. Boot time assignment

The ROM code uses the MCU SRAM1 to store the USB context during a boot on USB for Flash programming (with STM32CubeProgrammer).

In Cortex-A35 main processor mode, Cortex-A35 FSBL (TF-A BL2) uses SRAM1 during cold boot for:

• DDR firmware loading
• mbedTLS heap
• OTP shadow

3.1.1. On STM32MP21x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Core/RAM	SRAM	SRAM1	✓	✓	☐	Used during cold boot by TF-A BL2 for DDR firmware loading

3.1.2. On STM32MP23x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Core/RAM	SRAM	SRAM1	✓	✓	☐	Used during cold boot by TF-A BL2 for DDR firmware loading
		SRAM2		☐	☐

3.1.3. On STM32MP25x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Core/RAM	SRAM	SRAM1	✓	✓	☐	Used during cold boot by TF-A BL2 for DDR firmware loading
		SRAM2		☐	☐

3.2. Runtime assignment

In Cortex-A35 main processor mode, Cortex-A35 Secure OS(OP-TEE) uses SRAM1 for:

• OTP shadow

3.2.1. On STM32MP21x lines 

Click on to expand or collapse the legend...

STM32MP21 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP21 reference manuals.

Domain	Peripheral	Runtime allocation					Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)
Core/RAM	SRAM	SRAM1	☑OP-TEE ☐BL31	☐	☐	☐	OP-TEE populate OTP shadow region

3.2.2. On STM32MP23x lines 

Click on to expand or collapse the legend...

STM32MP23 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP23 reference manuals.

Domain	Peripheral	Runtime allocation					Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)
Core/RAM	SRAM	SRAM1	☑OP-TEE ☐BL31	☐	☐	☐	OP-TEE populate OTP shadow region
		SRAM2	☐OP-TEE ☐BL31	☐	☐	☐

3.2.3. On STM32MP25x lines 

Click on to expand or collapse the legend...

STM32MP25 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Runtime allocation						Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)	Cortex-M0+ (STM32Cube)
Core/RAM	SRAM	SRAM1	☑OP-TEE ☐BL31	☐	☐	☐		OP-TEE populate OTP shadow region
		SRAM2	☐OP-TEE ☐BL31	☐	☐	☐

4. Software frameworks and drivers

Below are listed the software frameworks and drivers using the SRAM peripheral for the embedded software components listed in the above tables.

• Linux: reserved memory, that is used by the dmaengine (for DMA buffers management) or RPMsg for interprocess communication with the coprocessor
• OP-TEE: OP-TEE
• STM32Cube: STM32Cube
• TF-M: TF-M

The default assignment set in STMicroelectronics distribution is in line with the platform memory mapping that can be adapted by the platform user.

5. How to assign and configure the peripheral

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

• partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
• HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

Cortex^®

Board support package

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Microcontroller unit (MCUs have internal flash memory and are intended to operate with a minimum amount of external support ICs. They commonly are a self-contained, system-on-chip (SoC) designs.)

Flash memory shortened to gain space in titles, tables and block diagrams

First stage boot loader

Doubledata rate (memory domain)

One time programmed

Read only memory

Trusted firmware for Arm^® Cortex^®-A

Boot loader stage 2

Das U-Boot -- the universal boot loader (see U-Boot)

Random access memory (Early computer memories generally hadserial access. Memories where any given address can be accessed when desired were then called "random access" to distinguish them from the memories where contents can only be accessed in a fixed order. The term is used today for volatile random-acces ssemiconductor memories.)

Operating system

Open portable trusted execution environment

Linux^® is a registered trademark of Linus Torvalds.

Hardware abstraction layer

Cortex^®

Board support package

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Microcontroller unit (MCUs have internal flash memory and are intended to operate with a minimum amount of external support ICs. They commonly are a self-contained, system-on-chip (SoC) designs.)

Flash memory shortened to gain space in titles, tables and block diagrams

First stage boot loader

Doubledata rate (memory domain)

One time programmed

Read only memory

Trusted firmware for Arm^® Cortex^®-A

Boot loader stage 2

Das U-Boot -- the universal boot loader (see U-Boot)

Random access memory (Early computer memories generally hadserial access. Memories where any given address can be accessed when desired were then called "random access" to distinguish them from the memories where contents can only be accessed in a fixed order. The term is used today for volatile random-acces ssemiconductor memories.)

Operating system

Open portable trusted execution environment

Linux^® is a registered trademark of Linus Torvalds.

Hardware abstraction layer

Flash memories combine high density and cost effectiveness of EPROMs with the electrical erasability of EEPROMs. For this reason, the Flash memory market is one of the most exciting areas of the semiconductor industry today and new applications requiring in system reprogramming, such as cellular telephones, automotive engine management systems, hard disk drives, PC BIOS software for Plug & Play, digital TV, set top boxes, fax and other modems, PC cards and multimedia CD-ROMs, offer the prospect of very high volume demand.