1. Article purpose[edit source]
This article introduces STM32CubeMP2 Package (a.k.a., 'STM32CubeMP2) architecture based on the Arm® Cortex®-M33 processor, acting as coprocessor of the Arm® Cortex®-A35.
- Refer to STM32CubeMP2 Package - Getting started article to get started.
2. Architecture overview[edit source]
The STM32CubeMP2 Package gathers together, in a single package, all the generic embedded software components required to develop applications on top of Arm® Cortex®-M33 microprocessors.
On top of the hardware, the STM32CubeMP2 Package solution is built around three levels of software components:
- Level 0: drivers
- Level 1: middleware
- Level 2: board demonstrations
These levels interact easily with each other. It also includes two common components, CMSIS and Utilities, which interact with all three levels.
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3. Level 0 (Drivers)[edit source]
This level is divided into three software components:
- Hardware abstraction layer (HAL)
- Low layer (LL)
- Board support package (BSP)
3.1. HAL drivers[edit source]
The HAL drivers provide the low-level drivers and the hardware interfacing methods to interact with the upper layers (application, libraries, and stacks). They provide generic, multi-instance, and function-oriented APIs, which simplify user application implementation by providing ready-to-use processes.
For example, for the communication peripherals (I2C, UART, etc.), they include APIs allowing the initialization and configuration of the peripheral, management of data transfer based on polling, interrupt, or DMA process, and handling of communication errors that may arise during communication.
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3.1.1. HAL drivers overview[edit source]
The HAL APIs layer is composed of native and extended API sets. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement their functions without in-depth knowledge about the used STM32 device. This improves the library code reusability and guarantees easy portability to other devices and STM32 families.
Contrary to the low-layer drivers (see Low Layer section), the HAL ones are functionality-oriented and not internal peripheral-oriented. For example, for the timer peripheral, the APIs could be split into several categories following the functions offered by the internal peripherals (basic timer, capture, PWM, etc.).
The HAL drivers are a set of common APIs with a high compliance level with most of the clients available on the market (stacks) called native APIs. They also embed some extended functionalities for special services or a combination of several features offered by the STM32 peripherals.
The HAL drivers APIs are split into two categories:
- Generic APIs: provide common and generic functions to all the STM32 series.
- Extension APIs: provide specific customized functions for a specific family or a specific part number.
3.1.2. List of HAL drivers[edit source]
The list of HAL drivers available for STM32MP25x lines is accessible in HAL drivers.
3.2. LL drivers[edit source]
The Low Layer (LL) drivers offer a fast, lightweight, expert-oriented layer that is closer to the hardware than the HAL. The LL APIs are available only for a set of peripherals.
3.2.1. LL drivers overview[edit source]
The Low Layer (LL) drivers are part of the STM32CubeMPU firmware HAL that provides a basic set of optimized and one-shot services. Unlike the HAL drivers, the LL drivers are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product.
The Low Layer (LL) drivers are designed to offer the following features:
- A new set of inline functions for direct and atomic register access
- One-shot operations that can be used by the HAL drivers or from the application level
- Fully independent from HAL and can be used in standalone usage (without HAL drivers)
- Full feature coverage of all the supported peripherals
3.2.2. List of LL drivers[edit source]
The list of LL drivers available for STM32MP25x lines is accessible in LL drivers.
3.3. BSP drivers[edit source]
The BSP drivers are firmware components based on the HAL drivers and provide a set of APIs related to the hardware components in the evaluation boards that come with the STM32CubeMPU Package. All examples and applications provided with the STM32CubeMPU Package are based on these BSP drivers.
3.3.1. BSP drivers overview[edit source]
The BSP architecture proposes a new model that prevents some standard library weaknesses and provides more features:
- Portable external resources code (components): the external components could be used by all STM32 families,
- Multiple use of hardware resources without duplicated initialization: example: I2C physical layer could be used for several EVAL drivers,
- Intuitive functionalities based on high-level use case,
- Portable BSP drivers for different external devices.
3.3.2. List of BSP drivers[edit source]
The BSP drivers offer a set of APIs relative to the hardware components available in the hardware boards (LEDs, buttons, and COM port). Refer to BSP_drivers
4. Level 1 (Middleware)[edit source]
Middleware components are a set of libraries providing a set of services. STM32CubeMP2 Package offers three main components:
- OpenAMP,
- FreeRTOS,
- USB power delivery.
Each middleware component is mainly composed of:
- Library core: this is the core of a component; it manages the main library state machine and the data flow between the several modules.
- Interface layer: the interface layer is generally used to link the component core with the lower layers, such as the HAL and the BSP drivers.
4.1. OpenAMP[edit source]
OpenAMP [1] is a library implementing the remote processor service framework (RPMsg) which is a messaging mechanism to communicate with a remote processor.
- Load and control Arm® Cortex®-M33 firmware
- Inter-processor communication
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4.2. FreeRTOS[edit source]
FreeRTOS [2] is a Free Real Time Operating System (RTOS). The FreeRTOS offers preemptive real-time performance with optimized context switch and interrupt times, enabling fast, highly predictable response times.
It includes the following main features:
- Small memory fingerprint
- High portability
- Multithread management
- Preemptive scheduling
- Fast interrupt response
- Extensive inter-process communication
- Synchronization facilities
- Tickless operation during low-power mode
- Open-source standard
- CMSIS compatibility layer
5. Level 2 (Boards demonstrations)[edit source]
The Boards demonstrations level is composed of a single layer, which provides all examples and applications. It also includes all STM32CubeIDE projects for each supported board as well as templates source files.
There are four kinds of projects demonstrating different usages of software APIs from Level 0 (Drivers) and Level 1 (Middleware):
- Examples projects: show how to use HAL APIs and Low Layer drivers (if any) with very basic usage of the BSP layer (buttons and LEDs in general).
- Applications projects: show how to use the middleware components (Level 1) and how to integrate them with the hardware and BSP/HAL layers (Level 0). These applications could be hybrid and use several other middleware components.
- Demonstrations projects: show how to integrate and run a maximum number of peripherals and middleware stacks to showcase the product features and performance.
- Templates projects: a very basic user application including STM32CubeIDE project files, which can be used to start a custom project.
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6. Utilities[edit source]
The Utilities is a set of common utilities and services offered by STM32CubeMP2 Package and is composed of different components :
└── Utilities
└── ResourcesManager Services for coprocessing in multi-core devices.
ResourceManager provides 2 APIs:
ResMgr_Status_t ResMgr_Request(ResMgr_Res_Type_t res_type, uint8_t res_num);
ResMgr_Status_t ResMgr_Release(ResMgr_Res_Type_t res_type, uint8_t res_num);
- The idea of the ResMgr_Request() API is to check and allocate a H/W resource (if available) for use by Cortex-M. This allocation could be shareable or exclusive as defined by the resource isolation framework (RIF) configuration.
- Corresponding ResMgr_Release() API is for releasing the reservation of resource done by the Request API.
7. CMSIS[edit source]
The Cortex microcontroller software interface standard (CMSIS) is a vendor-independent hardware abstraction layer for the Arm® Cortex®-M33 processor series.
- Refer to CMSIS[3] to get more information on CMSIS component.
The CMSIS component also provides specific common resources for device support. It enables consistent and simple software interfaces to the processor and peripherals, simplifying software reuse, reducing the learning curve for microcontroller developers, and reducing the time to market for new devices.
This vendor part is called CMSIS Device and it provides an interrupt list, peripheral registers description, and associated defines for all registers' bitfields.
- CMSIS structure overview:
├── CMSIS │ ├── Core │ │ ├── Include │ │ └── Template │ ├── Core_A │ │ ├── Include │ │ └── Template │ ├── Device CMSIS Device │ │ └── ST │ │ │ └── STM32MP2xx Common resources for STM32MP25x lines │ ├── docs │ │ ├── Core │ │ ├── Core_A │ │ ├── DAP │ │ ├── Driver │ │ ├── DSP │ │ ├── General │ │ ├── index.html │ │ ├── Pack │ │ ├── RTOS │ │ ├── RTOS2 │ │ ├── SVD │ │ └── Zone │ ├── DSP │ │ ├── Examples │ │ ├── Include │ │ └── Source │ ├── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm23.h │ │ ├── core_cm33.h │ │ ├── core_cm3.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h │ ├── LICENSE.txt │ ├── README.md │ ├── RTOS │ │ └── Template │ └── RTOS2 │ ├── Include │ ├── Source │ └── Template
- CMSIS Device structure :
Device/
└── ST
└── STM32MP2xx
├── Include
│ ├── RTE_Components.h
│ ├── stm32mp251axx_cm33.h
│ ├── stm32mp251cxx_cm33.h
│ ├── stm32mp251dxx_cm33.h
│ ├── stm32mp251fxx_cm33.h
│ ├── stm32mp253axx_cm33.h
│ ├── stm32mp253cxx_cm33.h
│ ├── stm32mp253dxx_cm33.h
│ ├── stm32mp253fxx_cm33.h
│ ├── stm32mp255axx_cm33.h
│ ├── stm32mp255cxx_cm33.h
│ ├── stm32mp255dxx_cm33.h
│ ├── stm32mp255fxx_cm33.h
│ ├── stm32mp257axx_cm0.h
│ ├── stm32mp257axx_cm33.h
│ ├── stm32mp257cxx_cm33.h
│ ├── stm32mp257dxx_cm33.h
│ ├── stm32mp257fxx_cm33.h
│ ├── stm32mp2xx.h
│ ├── system_stm32mp2xx.h
│ └── Templates_TZ
│ └── partition_stm32mp2xx.h
└── Source
└── Templates
├── gcc
│ ├── linker
│ │ ├── stm32mp23xx_DDR_m33_ns.ld
│ │ ├── stm32mp23xx_RETRAM_m33_s.ld
│ │ └── stm32mp2xx_DDR_m33_ns.ld
│ ├── startup_stm32mp251axx_m33.s
│ ├── startup_stm32mp251cxx_m33.s
│ ├── startup_stm32mp251dxx_m33.s
│ ├── startup_stm32mp251fxx_m33.s
│ ├── startup_stm32mp253axx_m33.s
│ ├── startup_stm32mp253cxx_m33.s
│ ├── startup_stm32mp253dxx_m33.s
│ ├── startup_stm32mp253fxx_m33.s
│ ├── startup_stm32mp255axx_m33.s
│ ├── startup_stm32mp255cxx_m33.s
│ ├── startup_stm32mp255dxx_m33.s
│ ├── startup_stm32mp255fxx_m33.s
│ ├── startup_stm32mp257axx_m33.s
│ ├── startup_stm32mp257cxx_m33.s
│ ├── startup_stm32mp257dxx_m33.s
│ ├── startup_stm32mp257fxx_m33.s
│ ├── startup_stm32mp257xx_m33.s
│ └── startup_stm32mp2xx_m33_ns.S
├── mmu_lpae_stm32mp2xx.c
├── system_stm32mp2xx_m33.c
├── system_stm32mp2xx_m33_ns.c
└── system_stm32mp2xx_m33_s.c
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8. References[edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 