How to define your low-power strategy

Applicable for

STM32MP13x lines, STM32MP15x lines, STM32MP25x lines

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1. Purpose

This article proposes some guidelines in order to determine the best low-power strategy for your STM32 MPU product.

2. On STM32MP13x lines 

2.1. STM32MP13 power supplies

It is important to understand the perimeter of the three STM32MP13 main power supplies:

• V_DD supplies I/Os and analog components such as reset, power management, oscillators and PLLs. V_DD is present as far as the STM32MP13 is not in Off or VBAT mode. For a given system, V_DD voltage is fixed and usually chosen between 1.8 V to 3.3 V typical.
• V_DDCORE supplies the digital core domain, except the Arm^® Cortex^®-A7 CPU, and must be present after V_DD at start up. Depending on the system low-power mode, V_DDCORE voltage varies between switched off (0 V), the retention voltage (0.9 V) and the nominal voltage (1.25 V). The mapping of these voltage levels to the low-power modes is shown in the next paragraph.
• V_DDCPU supplies the Arm^® Cortex^®-A7 CPU, and must be present after V_DD at start up. There is no precedence constraint between this supply and V_DDCORE. Depending on the system low-power mode, V_DDCCPU voltage varies between switched off (0 V), the retention voltage (0.9 V) and the nominal voltage (1.25 V). The mapping of these voltage levels to the low-power modes is shown in the next paragraph.

For more information, refer to the PWR chapter of the STM32MP13 Reference Manual and to the STM32MP13 Datasheet.

2.2. STM32MP13 low-power modes

Starting from the Run mode, various actions can be taken to reduce the processor power consumption when all tasks have been completed:

• Stop the high-speed clock sources (PLLs/HSI/HSE/CSI): this corresponds to the Stop mode where the V_DDCORE and V_DDCPU external regulators are kept at their nominal voltages. The regulators can even be switched in low-power mode in order to reduce their power consumptions: this is the LP-Stop mode.
• Stop the high-speed clock sources (PLLs/HSI/HSE/CSI) and reduce V_DDCORE and V_DDCPU voltages to their retention values: this is the LPLV-Stop mode, that enables to consume low power while maintaining the content of all the registers and internal memories.
• Stop the high-speed clock sources (PLLs/HSI/HSE/CSI), reduce V_DDCORE voltage to its retention value and switch off V_DDCPU: this is the LPLV-Stop2 mode, that enables to consume the minimum power while maintaining the content of all the registers and internal memories, except the CPU sub-system ones.
• Stop the high-speed clock sources (PLLs/HSI/HSE/CSI) and switch off V_DDCORE and V_DDCPU: this is the Standby mode, where the content of all registers and internal memories is lost, apart from the ones that are in V_SW domain that is supplied by V_DD (when present) or V_BAT (in VBAT mode). In particular, notice that the Backup registers and the BKPSRAM are in the V_SW domain. Please also note that PWR and RCC both have some registers in the V_SW (kept during Standby) and V_DD (lost during Standby) domains.

One or several wake-up source(s) are used to exit from the above low-power modes and come back to Run mode. Not all internal peripherals are able to wake up from low-power modes. Table Functionalities depending on system operating mode located in the PWR chapter of the STM32MP13 Reference Manual, shows the wake-up capability of each peripheral. This is summarized in the figure in the following paragraph.

When the processor is put in one of these low-power modes, the external RAM (DDR) is usually put in Self-Refresh mode in order to keep its content whereas most of the STM32MP13 is no more active (no more clock generated for the DDR, no more Auto-refresh commands). This extra power consumption has to be considered at system level and depends on the selected DDR memory (refer to your memory provider datasheet).

The main side effect of using low-power modes is the wake-up time required to restore the system to a full running state (Run mode): the deepest you slept and the longest it needs to wake up. The next chapter illustrates this in order to allow you to make the best choice for your product.

Refer to the AN5565 document for a deeper explanation of the low-power mode characteristics and dynamics.
Refer to the Power overview to discover the corresponding software architecture that enable using those modes with OpenSTLinux.

2.3. STM32MP13 low-power strategy

2.3.1. Overview

The figure below shows, for each low-power mode:

• The peripherals that can be used as wake-up sources (grey boxes)
• The STM32MP13 typical power consumption (on the left)
• The system wake-up times in various configurations (on the right)

2.3.2. STM32MP13 wake-up time interpretation

Warning

External factors, such as a ONKEY that would be debounced before reaching the STM32MP13 wake up pin, may influence the measurements given in the figure above and must be taken into account:

• For Arm^® Cortex^®-A7 core:
  • The wake-up times given in the above figure correspond to a typical OpenSTLinux distribution (around 7-Mbyte uImage, 600-Mbyte Weston rootfs, 35-second cold boot time)

3. On STM32MP15x lines 

3.1. STM32MP15 power supplies

It is important to understand the perimeter of the two STM32MP15 main power supplies:

• V_DD supplies I/Os and analog components such as reset, power management, oscillators and PLLs. V_DD is present as far as the STM32MP15 is not in Off or VBAT mode. For a given system, V_DD voltage is fixed and usually chosen between 1.8 V to 3.3 V typical.
• V_DDCORE supplies the digital core domain and must be present after V_DD at start up. Depending on the system low-power mode, V_DDCORE voltage varies between switched off (0 V), the retention voltage (0.9 V) and the nominal voltage (1.2 V). The mapping of these voltage levels to the low-power modes is shown in the next paragraph.

For more information, refer to the PWR chapter of the STM32MP15 Reference Manual and to the STM32MP15 Datasheet.

3.2. STM32MP15 low-power modes

Starting from the Run mode, various actions can be taken to reduce the processor power consumption when all tasks have been completed:

• Stop the high-speed clock sources (PLLs/HSI/HSE/CSI): this corresponds to the Stop mode where the V_DDCORE external regulator is kept at its nominal voltage. The regulator can even be switched in low-power mode in order to reduce its power consumption: this is the LP-Stop mode.
• Stop the high-speed clock sources (PLLs/HSI/HSE/CSI) and reduce V_DDCORE voltage to its retention value: this is the LPLV-Stop mode, that enables to consume the minimum power while maintaining the content of all the registers and internal memories.
• Stop the high-speed clock sources (PLLs/HSI/HSE/CSI) and switch off V_DDCORE: this is the Standby mode, where the content of all registers and internal memories is lost, apart from the ones that are in V_SW domain that is supplied by V_DD (when present) or V_BAT (in VBAT mode). In particular, notice that the Backup registers, the BKPSRAM and the RETAM are in the V_SW domain. Please also note that PWR and RCC both have some registers in the V_SW (kept during Standby) and V_DD (lost during Standby) domains.

One or several wake-up source(s) are used to exit from the above low-power modes and come back to Run mode. Not all internal peripherals are able to wake up from low-power modes. Table Functionalities depending on system operating mode located in the PWR chapter of the STM32MP15 Reference Manual, shows the wake-up capability of each peripheral. This is summarized in the figure in the following paragraph.

When the processor is put in one of these low-power modes, the external RAM (DDR) is usually put in Self-Refresh mode in order to keep its content whereas most of the STM32MP15 is no more active (no more clock generated for the DDR, no more Auto-refresh commands). This extra power consumption has to be considered at system level and depends on the selected DDR memory (refer to your memory provider datasheet).

The main side effect of using low-power modes is the wake-up time required to restore the system to a full running state (Run mode): the deepest you slept and the longest it needs to wake up. The next chapter illustrates this in order to allow you to make the best choice for your product.

Refer to the AN5109 document for a deeper explanation of the low-power mode characteristics and dynamics.
Refer to the Power overview to discover the corresponding software architecture that enable using those modes with OpenSTLinux.

3.3. STM32MP15 low-power strategy

3.3.1. Overview

The figure below shows, for each low-power mode:

• The peripherals that can be used as wake-up sources (grey boxes)
• The STM32MP15 typical power consumption (on the left)
• The system wake-up times in various configurations (on the right)

3.3.2. STM32MP15 wake-up time interpretation

Warning

External factors, such as a ONKEY that would be debounced before reaching the STM32MP15 wake up pin, may influence the measurements given in the figure above and must be taken into account:

• For Arm^® Cortex^®-A7 core:
  • The wake-up times given in the above figure correspond to a typical OpenSTLinux distribution (around 7-Mbyte uImage, 600-Mbyte Weston rootfs, 30-second cold boot time)
• For the Arm^® Cortex^®-M4 core:
  • The wake-up times correspond to the return to the software execution, so your application extra time has to be added to those figures, which are taken from the STM32MP15 datasheets.
  • The RETRAM and SRAM remain supplied in (LP-)Stop and LPLV-Stop modes, so the Cortex-M4 firmware code and data can use them.
  • The RETRAM remains supplied in Standby mode, and can hence be used to store the code of a size limited firmware that would be executed at wake-up. Once woken up, the firmware can use again the SRAM for data storing and the application running on the Cortex-A7 core could even reload some services (code) in SRAM.

Information

The core that is started on wake up from Standby is selected thanks to the MPU_BEN (Cortex-A7) and MCU_BEN (Cortex-M4) bits in RCC_MP_BOOTCR. Disabling both MPU_BEN and MCU_BEN is equivalent to enabling MPU_BEN. Enabling MPU_BEN is the nominal case. Enabling MCU_BEN requires to be aware of the ES0438 errata sheet following items: RCC security settings for Cortex-M4 access are not kept upon wake up from Standby Wake-up pin flags cleared at Standby mode exit with MCU_BEN high and MPU_BEN low Enabling both MPU_BEN and MCU_BEN is not recommended because race condition may occur on shared resources between each core (Cortex-A7 boot chain, including the ROM code, and Cortex-M4 firmware)

4. On STM32MP25x lines 

4.1. STM32MP25 power supplies

It is important to understand the perimeter of the STM32MP25 main power supplies:

• V_DD supplies the I/Os and the V_DD domain and V_DDA18AON supplies the system analog such as reset, power management, oscillators and OTP. V_DD and V_DDA18AON are present as far as the STM32MP25 is not in Off or VBAT mode. For a given system, V_DD voltage is fixed and usually chosen between 1.8 V to 3.3 V typical.
• V_DDCORE supplies the digital core domain, except the Arm^® Cortex^®-A35 CPU, and must be present after V_DD at start up. Depending on the system low-power mode, V_DDCORE voltage varies between switched off (0 V), the retention voltage (0.67 V) and the nominal voltage (0.82 V). The mapping of these voltage levels to the low-power modes is shown in the next paragraph.
• V_DDCPU supplies the Arm^® Cortex^®-A35 CPU, and must be present after V_DD at start up. There is no precedence constraint between this supply and V_DDCORE. Depending on the system low-power mode, V_DDCCPU voltage varies between switched off (0 V), the retention voltage (0.67 V), the nominal voltage (0.8 V) and the overdrive voltage (0.9 V). The mapping of these voltage levels to the low-power modes is shown in the next paragraph.
• V_DDGPU supplies the GPU domain supply. Depending on the GPU mode, V_DDGPU voltage varies between switched off (0 V), the retention voltage (0.67 V) and the nominal voltage (0.8 V) and the overdrive voltage (0.9 V).
• V_DDIOx supplies the independent I/Os domain 1 to 4

For more information, refer to the PWR chapter of the STM32MP25 Reference Manual and to the STM32MP25 Datasheet.

4.2. STM32MP25 low-power modes

Various actions can be taken to reduce the STM32MP25 power consumption.

In Run1 mode, the user can:

• slow down system clocks and limit V_DDCPU at their nominal voltages (no more overdrive),
• switch off the supplies and clocks when the associated devices are not used,
  for example V_DDGPU is switched off when GPU is stopped.

Starting from the Run1 mode, you can select a low-mode mode when all tasks have been completed and CPU1 do not need to execute code (when waiting for an external event):

• Stop the CPU1 = Cortex A35 and V_DDCPU external regulators, the Cortex-M33 and system D2 domain is still powered: this is Run2.
• Stop the system clock (including any PLL, and the system bus matrix clocks): this corresponds to the Stop1 mode where the V_DDCORE and V_DDCPU external regulators are kept at their nominal voltages.
  The external regulators are allowed (through PWR_LP pins) to enter in low-power mode to reduce their power consumption: this is the LP-Stop1 mode.
• Stop the system clock and reduce V_DDCORE and V_DDCPU voltages to their retention values: this is the LPLV-Stop1 mode, that enables to consume low power while maintaining the content of all the registers and internal memories, including the CPU1 sub-system.
• Stop the system clock and switch off V_DDCPU: this is the Stop2 mode.
  The external regulators are allowed (through PWR_LP pins) to enter in low-power mode to reduce their power consumption: this is the LP-Stop2 mode.
• Stop the system clock, switch off V_DDCPU and reduce V_DDCORE voltages to their retention values: this is the LPLV-Stop2 mode, that enables to consume the minimum power while maintaining the content of all the registers and internal memories, except the CPU sub-system ones.
• Stop the system clock and switch off V_DDCORE and V_DDCPU: where the content of all registers and internal memories is lost, apart from the ones that are in V_SW domain that is supplied by:
  • V_DD when present, this is the Standby1 mode when D3 domain is preserved or Standby2 mode (without D3 domain, the EXTI2 wake-up sources are not supported),
  • V_BAT when V_DD is switched off, this is the V_BAT modes (V_BAT1 with D3 domain or V_BAT2).

One or several wake-up source(s) are used to exit from the above low-power modes and come back to Run1 mode. Not all internal peripherals are able to wake up from low-power modes. Table 94. Functionalities depending on system operating mode located in the PWR chapter of the STM32MP25 Reference Manual, shows the wake-up capability of each peripheral.

In all these low power modes, the D3 domain, containing the Cortex-M0+ (CPU3), the Backup registers and the BKPSRAM, some peripherals and a small part of the system control (including the EXTI2 and some registers of PWR and RCC) are in the V_SW domain and is still supplied by V_DDCORE or an internal backup regulator powered by V_BAT. So their contents are kept, even if the D3 domain is in SStandby mode (D3 domain is in power down) in Standby2 and V_BAT2 modes.

When the processor is put in one of these low-power modes, the DDR controller put the external RAM (DDR) in Self-Refresh mode (no more clock generated for the DDR, no more Auto-refresh commands) in order to keep its content whereas most of the STM32MP25 is no more active and the Cortex-M33 firmware cannot be executed in DDR but only in STM32MP2 SRAM internal memory. The DDR power consumption in Self-Refresh mode has to be considered and depends on the selected DDR memory (refer to your memory provider datasheet).

For power off request, the Standby2 mode or the V_BAT modes can be used to keep the V_SW domain, for example to preserve content of BKPSRAM and backup registers, but the supplies associated to DDR are switched off and DDR content is lost.

The low-power mode of external regulators requested through PWR_LP pins must be defined. This signal is used to request a regulator or a peripheral to enter low-voltage and/or low-power state. For example, you can deactivate the VTT_DRR supply with PWRCTRL1 pins of STPMIC25.

The main side effect of using low-power modes is the wake-up time required to restore the system to a full running state (Run1 mode): the deepest you slept and the longest it needs to wake up.

OpenSTLinux 5.1.0 don't support all these modes, for example Run2 is not supported because the Cortex M33 firmware is expected running in DDR and only the boot on CPU1 = Cortex A35 with "legacy mode" (on wake up only CPU1 boots, CPU2 is kept in hold; see Power overview for supported modes).

Refer to the AN5726 document for a deeper explanation of the low-power mode characteristics and dynamics.

Refer to the Power overview to discover the corresponding software architecture that enable using those modes with OpenSTLinux.

4.3. STM32MP25 low-power strategy

Refer to the Power overview to discover the corresponding software architecture that enable using those modes with OpenSTLinux.

Refer to the AN5726 document for a deeper explanation of the low-power mode characteristics and wake-up sources and typical power consumption.

Refer to the AN5729 document for impact on life time usage of power supply voltages.

Microprocessor unit

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Central processing unit

High speed internal oscillator (STM32 clock source) or High speed synchronous serial interface (MIPI^® Alliance standard)

High speed external oscillator (STM32 clock source)

Multi Speed Internal oscillator (STM32 clock source)

Low power (MIPI^® Alliance DSI standard)

Reset and clock control

Random access memory (Early computer memories generally hadserial access. Memories where any given address can be accessed when desired were then called "random access" to distinguish them from the memories where contents can only be accessed in a fixed order. The term is used today for volatile random-acces ssemiconductor memories.)

Doubledata rate (memory domain)

Microcontroller unit (MCUs have internal flash memory and are intended to operate with a minimum amount of external support ICs. They commonly are a self-contained, system-on-chip (SoC) designs.)

Read only memory

One time programmed

Graphics processing units

Microprocessor unit

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Central processing unit

High speed internal oscillator (STM32 clock source) or High speed synchronous serial interface (MIPI^® Alliance standard)

High speed external oscillator (STM32 clock source)

Multi Speed Internal oscillator (STM32 clock source)

Low power (MIPI^® Alliance DSI standard)

Reset and clock control

Random access memory (Early computer memories generally hadserial access. Memories where any given address can be accessed when desired were then called "random access" to distinguish them from the memories where contents can only be accessed in a fixed order. The term is used today for volatile random-acces ssemiconductor memories.)

Doubledata rate (memory domain)

Microcontroller unit (MCUs have internal flash memory and are intended to operate with a minimum amount of external support ICs. They commonly are a self-contained, system-on-chip (SoC) designs.)

Read only memory

One time programmed

Graphics processing units

Mobile Industry Processor Interface, open membership organization that includes leading companies in the mobile industry that share the objective of defining and promoting open specifications for interfaces inside mobile terminals, see MIPI^® Alliance standard web site https://www.mipi.org

Display serial interface (MIPI^® Alliance standard)