Arm Cortex-M4

Revision as of 07:59, 22 June 2022 by Registered User
Applicable for STM32MP15x lines

1. Article purpose[edit source]

The purpose of this article is to:

  • briefly introduce the Arm® Cortex®-M4 core and its main features
  • indicate the level of security supported by this processor

2. Peripheral overview[edit source]

The Arm Cortex-M4 is seen as a coprocessor on STM32MP15, where the Arm Cortex-A7 is the main processor that controls it. The Cortex-M4 is present across all the STM32MP15x lines.

2.1. Features[edit source]

The Cortex-M4 is a 32-bit processor that belongs to the Armv7E-M architecture family. Armv7E-M corresponds to the ARMv7-M architecture, with DSP extension. Among a wide range of features, it includes a memory protection unit (MPU) and a single-precision floating point unit (FPU).

Refer to the STM32MP15 reference manuals for the complete list of features.

2.2. Security support[edit source]

The Cortex-M4 does not support secure mode: it only supports a non-secure mode that defines the Cortex-M4 non-secure hardware execution context.

3. Peripheral usage and associated software[edit source]

3.1. Boot time[edit source]

The STM32CubeMP1 package execution startup on the Cortex-M4 coprocessor is controlled by the Cortex-A7, that is running the OpenSTLinux distribution.

The coprocessor startup can be done at two different stages of the boot chain:

Thanks to a specific OP-TEE trusted application (TA) running on the Arm® TrustZone and to the ETZPC peripheral, it is possible to authenticate the Cortex®-M4 firmware and install it on isolated MCU RAM to ensure its integrity during the execution. For details, please refer to How_to_protect_the_coprocessor_firmware article.

3.2. Runtime[edit source]

3.2.1. Overview[edit source]

The Cortex-M4 runs the STM32CubeMP1 package.

The Cortex-M4 operates as a coprocessor, either autonomously as any external microcontroller (such as an STM32F4) could, or communicating with the main processor (Cortex-A7) via the RPMsg communication pipe.

3.2.2. Software frameworks[edit source]

Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Ecosystem Cortex-M4 STM32CubeMP1 package

3.2.3. Peripheral configuration[edit source]

The Cortex-M4 configuration is done in two steps:

  1. As the main processor of the system, the Cortex-A7 (running OpenSTLinux distribution) first takes care of the initialization of all system resources: supplies, clock tree, and so on.
  2. The STM32CubeMP1 package then takes care of all the Cortex-M4 local configuration (NVIC, MPU, and so on). It can rely on the resource manager to modify system resources without interfering with the Cortex-A7.

3.2.4. Peripheral assignment[edit source]

The Cortex-M4 is the Cortex-A7's coprocessor, so it cannot assign peripheral to its usage but it manages all the peripherals assigned to its context.

4. How to go further[edit source]

Refer to the Arm website[1] for more detailed information on this core.

5. References[edit source]