1. Article purpose[edit source]
The purpose of this article is to explain how the TAMP backup registers are used by STM32MPU Embedded Software on STM32MP13.
2. Overview[edit source]
The STM32MP13 embeds 32 backup registers of 32 bits. A programmable border allows to split those backup registers into a secure and a non-secure groupa.
3. Backup registers usage[edit source]
This paragraph explains the default backup registers usage by the ROM code and STM32MPU Embedded Software distribution. Then, the next chapter shows the backup register mapping used to fulfill those needs.
3.1. Boot counter feature[edit source]
The BOOT_COUNTER is used by U-Boot to detect boot failures between its execution and before the complete Linux application initialization :
- It is incremented by U-Boot
- It is reset by the application
So, if U-Boot reads a non null value after a reset, this means that something went wrong at boot time and can be used to enter a fail safe mode.
3.2. Boot mode selection feature[edit source]
The BOOT_MODE register is used to propagate boot mode information from one component to the next boot stage, on cold boot or after a reset:
- The ROM code executes a serial boot if BOOT_MODE[7:0] is equal to 0xFF, as stated in the ROM code boot device selection strategy. In that case, the backup register is reset by the ROM code before proceeding with the serial boot mode. Other values are ignored by the ROM code.
- TF-A gets the selected boot device from the ROM code context in SYSRAM and writes it into BOOT_MODE[15:8] for U-Boot[1].
- U-Boot uses the BOOT_MODE register to get TF-A and Linux kernel (as explained in the next bullet) information[2] in order to select the wished boot mode (among "NORMAL", "STM32PROG", ...[1]) and build the appropriate "chosen" node in the device tree. This device tree is given to the Linux kernel for its start up, as explained in "Runtime configuration" paragraph in Documentation/devicetree/usage-model.rst .
- The Linux kernel can force a reboot-mode writing into the BOOT_MODE register. This writing is done via the "reboot" Linux command, that is configured via the compatible "syscon-reboot-mode" in the device tree [2].
4. Memory mapping[edit source]
The table below shows the backup register mapping used by STM32MPU Embedded Software.
The TAMP backup register base address is 0x5C00A100, corresponding to TAMP_BKP0R.
| TAMP register | Securitya | ROM / software register name | Comment |
|---|---|---|---|
| TAMP_BKP31R | Non-secure | M4_WAKEUP_AREA_HASH | SHA-256 value, see Cortex-M4 wake up feature |
| TAMP_BKP30R | Non-secure | ||
| TAMP_BKP29R | Non-secure | ||
| TAMP_BKP28R | Non-secure | ||
| TAMP_BKP27R | Non-secure | ||
| TAMP_BKP26R | Non-secure | ||
| TAMP_BKP25R | Non-secure | ||
| TAMP_BKP24R | Non-secure | ||
| TAMP_BKP23R | Non-secure | M4_WAKEUP_AREA_LENGTH | See Cortex-M4 wake up feature |
| TAMP_BKP22R | Non-secure | M4_WAKEUP_AREA_START | See Cortex-M4 wake up feature |
| TAMP_BKP21R | Non-secure | BOOT_COUNTER | See Boot counter feature |
| TAMP_BKP20R | Non-secure | BOOT_MODE | See Boot mode selection feature |
| TAMP_BKP19R | Non-secure | (Reserved for future use) | |
| TAMP_BKP18R | Non-secure | CORTEX_M_STATE | See Cortex-M4 management feature |
| TAMP_BKP17R | Non-secure | COPRO_RSC_TBL_ADDRESS | See Cortex-M4 management feature |
| TAMP_BKP16R | Non-secure | (Reserved for future use) | |
| TAMP_BKP15R | Non-secure | (Reserved for future use) | |
| TAMP_BKP14R | Non-secure | (Reserved for future use) | |
| TAMP_BKP13R | Non-secure | (Reserved for future use) | |
| TAMP_BKP12R | Non-secure | (Reserved for future use) | |
| TAMP_BKP11R | Non-secure | (Reserved for future use) | |
| TAMP_BKP10R | Non-secure | (Reserved for future use) | |
| TAMP_BKP9R | Secure | (Reserved for future use) | |
| TAMP_BKP8R | Secure | (Reserved for future use) | |
| TAMP_BKP7R | Secure | (Reserved for future use) | |
| TAMP_BKP6R | Secure | (Reserved for future use) | |
| TAMP_BKP5R | Secure | BRANCH_ADDRESS | See DDR and CPU wake up management feature |
| TAMP_BKP4R | Secure | MAGIC_NUMBER | See DDR and CPU wake up management feature |
| TAMP_BKP3R | Secure | M4_SECURITY_PERIMETER_EXTI3 | See Cortex-M4 wake up feature |
| TAMP_BKP2R | Secure | M4_SECURITY_PERIMETER_EXTI2 | See Cortex-M4 wake up feature |
| TAMP_BKP1R | Secure | M4_SECURITY_PERIMETER_EXTI1 | See Cortex-M4 wake up feature |
| TAMP_BKP0R | Secure | WAKEUP_SEC | See Cortex-M4 wake up feature |
a: the security border is configured by the Secure OS (look for "zone" in plat/st/stm32mp1/sp_min/sp_min_setup.c for TF-A SP-MIN or in core/arch/arm/plat-stm32mp1/main.c for OP-TEE), so the source code has to be modified if a different border is needed.