1. Article purpose[edit source]
The purpose of this article is to:
- briefly introduce the SPI peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit source]
The SPI peripheral is used to communicate with an external devices using the SPI (Serial Peripheral Interface).
A subset of the SPI instances supports the I2S audio protocol. These SPI/I2S peripherals can alternatively be used in audio applications, when they are configured as an I2S interface. Refer to peripheral usage chapter to check I2S feature support for each SPI instance.
2.1. SPI main features[edit source]
- Full-duplex, half-duplex and simplex synchronous modes.
- Slave and master modes.
2.2. I2S main features[edit source]
Only available for SPI supporting I2S mode.
- Full-duplex or simplex modes.
- Slave and master modes.
- Four audio protocols supported.
2.3. Specific features[edit source]
Some of the SPI peripheral characteristics depend on I2S support, as summarized in following table:
| SPI modes/features | I2S supported | I2S not supported |
|---|---|---|
| Rx & TxFIFO size (N) [x 8-bit] | 16 | 8 |
| Maximum configurable data size [bits] | 32 | 16 |
On STM32MP25x lines 
, spi8 has only a limited feature set compared to other 7 instances, with only 8 / 16 bits data size and shorter transfer size compared to other instances.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit source]
3.1.1. On STM32MP1 series[edit source]
The SPI peripheral is not used at boot time.
3.1.2. On STM32MP2 series[edit source]
Click on 
to expand or collapse the legend...
- ☐ means that the peripheral can be assigned to the given boot time context.
- ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 non-secure (U-Boot) | |||
| Low speed interface or audio |
SPI | SPI2S1 | ⬚ | ☐ | ||
| SPI2S2 | ⬚ | ☐ | ||||
| SPI2S3 | ⬚ | ☐ | ||||
| SPI4 | ⬚ | ☐ | ||||
| SPI5 | ⬚ | ☐ | ||||
| SPI6 | ⬚ | ☐ | ||||
| SPI7 | ⬚ | ☐ | ||||
| SPI8 | ⬚ | ☐ | ||||
3.2. Runtime assignment[edit source]
3.2.1. On STM32MP13x lines [edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP13 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| ||
|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
| Low speed interface or audio |
SPI | SPI2S1 | ☐ | ||
| SPI2S2 | ☐ | ||||
| SPI2S3 | ☐ | ||||
| SPI2S4 | ⬚ | ☐ | Assignment (single choice) | ||
| SPI5 | ⬚ | ☐ | Assignment (single choice) | ||
3.2.2. On STM32MP15x lines [edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| Low speed interface or audio |
SPI | SPI2S1 | ☐ | ☐ | Assignment (single choice) | |
| SPI2S2 | ☐ | ☐ | Assignment (single choice) | |||
| SPI2S3 | ☐ | ☐ | Assignment (single choice) | |||
| SPI4 | ☐ | ☐ | Assignment (single choice) | |||
| SPI5 | ☐ | ☐ | Assignment (single choice) | |||
| SPI6 | ⬚ | ☐ | Assignment (single choice) | |||
3.2.3. On STM32MP25x lines [edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 non-secure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 non-secure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| Low speed interface or audio |
SPI | SPI2S1 | ⬚OP-TEE | ☐ | ⬚ | ☐ | ||
| SPI2S2 | ⬚OP-TEE | ☐ | ⬚ | ☐ | ||||
| SPI2S3 | ⬚OP-TEE | ☐ | ⬚ | ☐ | ||||
| SPI4 | ⬚OP-TEE | ☐ | ⬚ | ☐ | ||||
| SPI5 | ⬚OP-TEE | ☐ | ⬚ | ☐ | ||||
| SPI6 | ⬚OP-TEE | ☐ | ⬚ | ☐ | ||||
| SPI7 | ⬚OP-TEE | ☐ | ⬚ | ☐ | ||||
| SPI8 | ⬚OP-TEE | ☐ | ⬚ | ☐ | ☐ | |||
4. Software frameworks and drivers[edit source]
Below are listed the software frameworks and drivers managing the SPI peripheral for the embedded software components listed in the above tables.
- Linux®: Linux SPI framework for SPI configured in SPI mode, and Linux ALSA framework for SPI configured in I2S mode (only for SPI supporting I2S feature)
- STM32Cube: HAL SPI driver for SPI configured in SPI mode. HAL I2S driver is not available for SPI configured in I2S mode.
5. How to assign and configure the peripheral[edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
When the Arm® Cortex®-A7 core operates in non-secure access mode, the SPI is controlled by the Linux kernel framework.
- SPI mode:
Refer to SPI framework to check how to drive SPI through Linux kernel.
- I2S mode:
Refer to I2S Linux driver to drive the SPI through Linux kernel ALSA framework. Refer to Soundcard configuration to configure it through the Linux kernel device tree[1].
6. References[edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 