DDRCTRL and DDRPHYC device tree configuration

Revision as of 16:31, 13 October 2023 by Registered User (→‎DT configuration examples: MP25 update)
Applicable for STM32MP13x lines, STM32MP15x lines

1. Article purpose[edit source]

This article explains how to configure the DDRCTRL and DDRPHYC internal peripherals from the first stage bootloader.

The configuration is performed using the device tree mechanism that provides a hardware description of the DDR subsystem (DDR controler and DDR PHY peripheral), and embeds the configuration used by the first stage bootloader to initialize the DDR before loading the second stage bootloader.

The DDR settings are only used in the device tree of the boot chain FSBL, that is, in the TF-A device tree for OpenSTLinux official delivery.

2. DT bindings documentation[edit source]

The DDR subsystem is a 'memory-controller' device represented by the device tree bindings documented below:

  • TF-A: docs/devicetree/bindings/memory-controllers/st,stm32mp1-ddr.txt"[1] on STM32MP15x lines More info.png and STM32MP13x lines More info.png
  • TF-A: docs/devicetree/bindings/memory-controllers/st,stm32mp2-ddr.txt"[2] on STM32MP25x lines More info.png

3. DT configuration[edit source]

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device-tree file split.

STM32CubeMX can be used to generate this DDR board device tree. Refer to How to configure the DT using STM32CubeMX for more details.

3.1. DT configuration (STM32 level)[edit source]

The STM32MP1 DDR node is located

  • for STM32MP13x lines More info.png in stm32mp131.dtsi [3]
  • for STM32MP15x lines More info.png in stm32mp151.dtsi [4]

see Device tree for further explanation.

Warning white.png Warning
This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end user.

For example: 

 		ddr: ddr@5a003000{
 			compatible = "st,stm32mp1-ddr";
 			reg = <0x5A003000 0x550 0x5A004000 0x234>;
 			clocks = <&rcc AXIDCG>,
 				 <&rcc DDRC1>,
 				 <&rcc DDRC2>,
 				 <&rcc DDRPHYC>,
 				 <&rcc DDRCAPB>,
 				 <&rcc DDRPHYCAPB>;
 			clock-names = "axidcg",
 				      "ddrc1",
 				      "ddrc2",
 				      "ddrphyc",
 				      "ddrcapb",
 				      "ddrphycapb";
 			status = "okay";
 		};

3.2. DT configuration (board level)[edit source]

The next attributes provide the DDR information and DDR settings; the values used by the FSBL to initialize the registers of the DDR subsystem (the DDR controller and the DDR PHY).

These value are generated by DDR tools included in STM32CubeMX.

The board configuration defines each configuration needed (DDR_...) and includes the STM32-level device tree.

3.2.1. On STM32MP1 series[edit source]

3.2.1.1. info[edit source]
  • st,mem-name: name for the DDR configuration, a simple string for information
  • st,mem-speed: DDR expected speed in kHz
  • st,mem-size: DDR mem size in bytes (used in SSBL and FSBL)
3.2.1.2. Controller register values[edit source]
  • st,ctl-reg: controller values depending on the DDR type (DDR3/LPDDR2/LPDDR3):
    • for STM32MP13x lines More info.png and for STM32MP15x lines More info.png 25 values are requested in this order: (MSTR MRCTRL0 MRCTRL1 DERATEEN DERATEINT PWRCTL PWRTMG HWLPCTL RFSHCTL0 RFSHCTL3 CRCPARCTL0 ZQCTL0 DFITMG0 DFITMG1 DFILPCFG0 DFIUPD0 DFIUPD1 DFIUPD2 DFIPHYMSTR ODTMAP DBG0 DBG1 DBGCMD POISONCFG PCCFG)
  • st,ctl-timing: controller values depending on the DDR frequency and timing parameters:
    • for STM32MP13x lines More info.png and for STM32MP15x lines More info.png 12 values are requested in this order: (RFSHTMG DRAMTMG0 DRAMTMG1 DRAMTMG2 DRAMTMG3 DRAMTMG4 DRAMTMG5 DRAMTMG6 DRAMTMG7 DRAMTMG8 DRAMTMG14 ODTCFG)
  • st,ctl-map: controller values depending on the address mapping:
    • for STM32MP13x lines More info.png and for STM32MP15x lines More info.png 9 values are requested in this order: (ADDRMAP1 ADDRMAP2 ADDRMAP3 ADDRMAP4 ADDRMAP5 ADDRMAP6 ADDRMAP9 ADDRMAP10 ADDRMAP11)
  • st,ctl-perf: controller values depending on performance and scheduling:
    • for STM32MP13x lines More info.png 11 values are requested in this order: (SCHED SCHED1 PERFHPR1 PERFLPR1 PERFWR1 PCFGR_0 PCFGW_0 PCFGQOS0_0 PCFGQOS1_0 PCFGWQOS0_0 PCFGWQOS1_0)
    • for STM32MP15x lines More info.png 17 values are requested in this order: (SCHED SCHED1 PERFHPR1 PERFLPR1 PERFWR1 PCFGR_0 PCFGW_0 PCFGQOS0_0 PCFGQOS1_0 PCFGWQOS0_0 PCFGWQOS1_0 PCFGR_1 PCFGW_1 PCFGQOS0_1 PCFGQOS1_1 PCFGWQOS0_1 PCFGWQOS1_1)
3.2.1.3. phy register values[edit source]
  • st,phy-reg: phy values depending on the DDR type: (DDR3/LPDDR2/LPDDR3):
    • for STM32MP13x lines More info.png 9 values are requested in this order: (PGCR ACIOCR DXCCR DSGCR DCR ODTCR ZQ0CR1 DX0GCR DX1GCR)
    • for STM32MP15x lines More info.png 11 values are requested in this order: (PGCR ACIOCR DXCCR DSGCR DCR ODTCR ZQ0CR1 DX0GCR DX1GCR DX2GCR DX3GCR)
  • st,phy-timing: phy values depending on the DDR frequency and timing parameters:
    • for STM32MP13x lines More info.png and for STM32MP15x lines More info.png 10 values are requested in this order: (PTR0 PTR1 PTR2 DTPR0 DTPR1 DTPR2 MR0 MR1 MR2 MR3)
  • st,phy-cal: phy cal depending on the DDR calibration or tuning. This parameter is optional: when it is absent, the built-in PHY calibration is done (see the next chapter for details); when it is present:
    • for STM32MP13x lines More info.png 6 values are requested in this order: (DX0DLLCR DX0DQTR DX0DQSTR DX1DLLCR DX1DQTR DX1DQSTR)
    • for STM32MP15x lines More info.png 12 values are requested in this order: (DX0DLLCR DX0DQTR DX0DQSTR DX1DLLCR DX1DQTR DX1DQSTR DX2DLLCR DX2DQTR DX2DQSTR DX3DLLCR DX3DQTR DX3DQSTR)
3.2.1.4. st,phy-cal value and DDR tuning[edit source]
Warning white.png Warning
It is strongly recommended not to fill the st,phy-cal property and then use the build-in PHY calibration.

By default, the st,phy-cal property is absent in device tree and the built-in PHY calibration is executed by the DDR driver to determine DXnDQTR and DXnDQSTR register values (with n = byte id, 0 to 3).

When st,phy-cal is present in device tree (e.g. when DDR_PHY_CAL_SKIP is defined), the built-in PHY calibration is skipped and the driver use the DXnDQTR and DXnDQSTR values defined in the device tree: they described the fine step delays used for DQ/DQS pin deskew and for eye centering.

See #How to configure the DT using STM32CubeMX and the dedicated application note[5] for further information.

3.2.2. On STM32MP2 series[edit source]

3.2.2.1. info[edit source]

Same as on STM32MP1 series

3.2.2.2. Controller register values[edit source]
  • st,ctl-reg: controller values depending on the DDR type (DDR3/DDR4/LPDDR4):
    • 48 values are requested in this order: (MSTR MRCTRL0 MRCTRL1 MRCTRL2 DERATEEN DERATEINT DERATECTL PWRCTL PWRTMG HWLPCTL RFSHCTL0 RFSHCTL1 RFSHCTL3 CRCPARCTL0 CRCPARCTL1 INIT0 INIT1 INIT2 INIT3 INIT4 INIT5 INIT6 INIT7 DIMMCTL RANKCTL RANKCTL1 ZQCTL0 ZQCTL1 ZQCTL2 DFITMG0 DFITMG1 DFILPCFG0 DFILPCFG1 DFIUPD0 DFIUPD1 DFIUPD2 DFIMISC DFITMG2 DFITMG3 DBICTL DFIPHYMSTR DBG0 DBG1 DBGCMD SWCTL SWCTLSTATIC POISONCFG PCCFG)
  • st,ctl-timing: controller values depending on the DDR frequency and timing parameters:
    • 20 values are requested in this order: (RFSHTMG RFSHTMG1 DRAMTMG0 DRAMTMG1 DRAMTMG2 DRAMTMG3 DRAMTMG4 DRAMTMG5 DRAMTMG6 DRAMTMG7 DRAMTMG8 DRAMTMG9 DRAMTMG10 DRAMTMG11 DRAMTMG12 DRAMTMG13 DRAMTMG14 DRAMTMG15 ODTCFG ODTMAP)
  • st,ctl-map: controller values depending on the address mapping:
    • 12 values are requested in this order: (ADDRMAP0 ADDRMAP1 ADDRMAP2 ADDRMAP3 ADDRMAP4 ADDRMAP5 ADDRMAP6 ADDRMAP7 ADDRMAP8 ADDRMAP9 ADDRMAP10 ADDRMAP11)
  • st,ctl-perf: controller values depending on performance and scheduling:
    • 21 values are requested in this order: (SCHED SCHED1 PERFHPR1 PERFLPR1 PERFWR1 SCHED3 SCHED4 PCFGR_0 PCFGW_0 PCTRL_0 PCFGQOS0_0 PCFGQOS1_0 PCFGWQOS0_0 PCFGWQOS1_0 PCFGR_1 PCFGW_1 PCTRL_1 PCFGQOS0_1 PCFGQOS1_1 PCFGWQOS0_1 PCFGWQOS1_1)
3.2.2.3. phy attributes[edit source]
  • st,phy-basic: basic entry values for the PHYINIT driver:
    • 19 values are requested in this order: (UIB_DRAMTYPE UIB_DIMMTYPE UIB_LP4XMODE UIB_NUMDBYTE UIB_NUMACTIVEDBYTEDFI0 UIB_NUMACTIVEDBYTEDFI1 UIB_NUMANIB UIB_NUMRANK_DFI0 UIB_NUMRANK_DFI1 UIB_DRAMDATAWIDTH UIB_NUMPSTATES UIB_FREQUENCY_0 UIB_PLLBYPASS_0 UIB_DFIFREQRATIO_0 UIB_DFI1EXISTS UIB_TRAIN2D UIB_HARDMACROVER UIB_READDBIENABLE_0 UIB_DFIMODE)
  • st,phy-advanced: advanced entry values for the PHYINIT driver:
    • 43 values are requested in this order: (UIA_LP4RXPREAMBLEMODE_0 UIA_LP4POSTAMBLEEXT_0 UIA_D4RXPREAMBLELENGTH_0 UIA_D4TXPREAMBLELENGTH_0 UIA_EXTCALRESVAL UIA_IS2TTIMING_0 UIA_ODTIMPEDANCE_0 UIA_TXIMPEDANCE_0 UIA_ATXIMPEDANCE UIA_MEMALERTEN UIA_MEMALERTPUIMP UIA_MEMALERTVREFLEVEL UIA_MEMALERTSYNCBYPASS UIA_DISDYNADRTRI_0 UIA_PHYMSTRTRAININTERVAL_0 UIA_PHYMSTRMAXREQTOACK_0 UIA_WDQSEXT UIA_CALINTERVAL UIA_CALONCE UIA_LP4RL_0 UIA_LP4WL_0 UIA_LP4WLS_0 UIA_LP4DBIRD_0 UIA_LP4DBIWR_0 UIA_LP4NWR_0 UIA_LP4LOWPOWERDRV UIA_DRAMBYTESWAP UIA_RXENBACKOFF UIA_TRAINSEQUENCECTRL UIA_SNPSUMCTLOPT UIA_SNPSUMCTLF0RC5X_0 UIA_TXSLEWRISEDQ_0 UIA_TXSLEWFALLDQ_0 UIA_TXSLEWRISEAC UIA_TXSLEWFALLAC UIA_DISABLERETRAINING UIA_DISABLEPHYUPDATE UIA_ENABLEHIGHCLKSKEWFIX UIA_DISABLEUNUSEDADDRLNS UIA_PHYINITSEQUENCENUM UIA_ENABLEDFICSPOLARITYFIX UIA_PHYVREF UIA_SEQUENCECTRL_0)
  • st,phy-mr: mode register entry values for the PHYINIT driver:
    • 12 values are requested in this order: (UIM_MR0_0 UIM_MR1_0 UIM_MR2_0 UIM_MR3_0 UIM_MR4_0 UIM_MR5_0 UIM_MR6_0 UIM_MR11_0 UIM_MR12_0 UIM_MR13_0 UIM_MR14_0 UIM_MR22_0)
  • st,phy-swizzle swizzling (i.e. signal/ball multiplexing) entry values for the PHYINIT driver:
    • 44 values are requested in this order: (UIS_SWIZZLE_0 UIS_SWIZZLE_1 UIS_SWIZZLE_2 UIS_SWIZZLE_3 UIS_SWIZZLE_4 UIS_SWIZZLE_5 UIS_SWIZZLE_6 UIS_SWIZZLE_7 UIS_SWIZZLE_8 UIS_SWIZZLE_9 UIS_SWIZZLE_10 UIS_SWIZZLE_11 UIS_SWIZZLE_12 UIS_SWIZZLE_13 UIS_SWIZZLE_14 UIS_SWIZZLE_15 UIS_SWIZZLE_16 UIS_SWIZZLE_17 UIS_SWIZZLE_18 UIS_SWIZZLE_19 UIS_SWIZZLE_20 UIS_SWIZZLE_21 UIS_SWIZZLE_22 UIS_SWIZZLE_23 UIS_SWIZZLE_24 UIS_SWIZZLE_25 UIS_SWIZZLE_26 UIS_SWIZZLE_27 UIS_SWIZZLE_28 UIS_SWIZZLE_29 UIS_SWIZZLE_30 UIS_SWIZZLE_31 UIS_SWIZZLE_32 UIS_SWIZZLE_33 UIS_SWIZZLE_34 UIS_SWIZZLE_35 UIS_SWIZZLE_36 UIS_SWIZZLE_37 UIS_SWIZZLE_38 UIS_SWIZZLE_39 UIS_SWIZZLE_40 UIS_SWIZZLE_41 UIS_SWIZZLE_42 UIS_SWIZZLE_43)

See #How to configure the DT using STM32CubeMX for further information.

3.3. DT configuration examples[edit source]

3.3.1. On STM32MP1 series[edit source]

3.3.1.1. Simple example[edit source]

You can add the DDR configuration node with (STM32MP15x lines More info.png example): 

  &ddr {
  	st,mem-name = "DDR3 2x4Gb 533MHz";
  	st,mem-speed = <533000>;
  	st,mem-size = <0x40000000>;
  
  	st,ctl-reg = <
  				0x00040401 /*MSTR*/
  				0x00000010 /*MRCTRL0*/
	  			0x00000000 /*MRCTRL1*/
  				0x00000000 /*DERATEEN*/
  				0x00800000 /*DERATEINT*/
  				0x00000000 /*PWRCTL*/
  				0x00400010 /*PWRTMG*/
  				0x00000000 /*HWLPCTL*/
  				0x00210000 /*RFSHCTL0*/
  				0x00000000 /*RFSHCTL3*/
  				0x00000000 /*CRCPARCTL0*/
  				0xC2000040 /*ZQCTL0*/
  				0x02050105 /*DFITMG0*/
  				0x00000202 /*DFITMG1*/
  				0x07000000 /*DFILPCFG0*/
  				0xC0400003 /*DFIUPD0*/
  				0x00000000 /*DFIUPD1*/
  				0x00000000 /*DFIUPD2*/
  				0x00000000 /*DFIPHYMSTR*/
  				0x00000001 /*ODTMAP*/
  				0x00000000 /*DBG0*/
  				0x00000000 /*DBG1*/
  				0x00000000 /*DBGCMD*/
  				0x00000000 /*POISONCFG*/
  				0x00000010 /*PCCFG*/
 	 >;
  
  	st,ctl-timing = <
  				0x0080008A /*RFSHTMG*/
  				0x121B2414 /*DRAMTMG0*/
  				0x000D041B /*DRAMTMG1*/
  				0x0607080E /*DRAMTMG2*/
  				0x0050400C /*DRAMTMG3*/
  				0x07040407 /*DRAMTMG4*/
  				0x06060303 /*DRAMTMG5*/
  				0x02020002 /*DRAMTMG6*/
  				0x00000202 /*DRAMTMG7*/
  				0x00001005 /*DRAMTMG8*/
  				0x000D041B /*DRAMTMG14*/
  				0x06000600 /*ODTCFG*/
  	>;
  
 	st,ctl-map = <
 				0x00080808 /*ADDRMAP1*/
 				0x00000000 /*ADDRMAP2*/
 				0x00000000 /*ADDRMAP3*/
 				0x00001F1F /*ADDRMAP4*/
 				0x07070707 /*ADDRMAP5*/
 				0x0F070707 /*ADDRMAP6*/
 				0x00000000 /*ADDRMAP9*/
 				0x00000000 /*ADDRMAP10*/
 				0x00000000 /*ADDRMAP11*/
 	>;
  
 	st,ctl-perf = <
 				0x00001201 /*SCHED*/
 				0x00001201 /*SCHED*/1
 				0x01000001 /*PERFHPR1*/
 				0x08000200 /*PERFLPR1*/
 				0x08000400 /*PERFWR1*/
 				0x00010000 /*PCFGR_0*/
 				0x00000000 /*PCFGW_0*/
 				0x02100B03 /*PCFGQOS0_0*/
 				0x00800100 /*PCFGQOS1_0*/
 				0x01100B03 /*PCFGWQOS0_0*/
 				0x01000200 /*PCFGWQOS1_0*/
 				0x00010000 /*PCFGR_1*/
 				0x00000000 /*PCFGW_1*/
 				0x02100B03 /*PCFGQOS0_1*/
 				0x00800000 /*PCFGQOS1_1*/
 				0x01100B03 /*PCFGWQOS0_1*/
 				0x01000200 /*PCFGWQOS1_1*/
 	>;
  
 	st,phy-reg = <
 				0x01442E02 /*PGCR*/
 				0x10400812 /*ACIOCR*/
 				0x00000C40 /*DXCCR*/
 				0xF200001F /*DSGCR*/
 				0x0000000B /*DCR*/
 				0x00010000 /*ODTCR*/
 				0x0000007B /*ZQ0CR1*/
 				0x0000CE81 /*DX0GCR*/
 				0x0000CE81 /*DX1GCR*/
 				0x0000CE81 /*DX2GCR*/
 				0x0000CE81 /*DX3GCR*/
 	>;
  
 	st,phy-timing = <
 				0x0022A41B /*PTR0*/
 				0x047C0740 /*PTR1*/
 				0x042D9C80 /*PTR2*/
 				0x369477D0 /*DTPR0*/
 				0x098A00D8 /*DTPR1*/
 				0x10023600 /*DTPR2*/
 				0x00000830 /*MR0*/
 				0x00000000 /*MR1*/
 				0x00000208 /*MR2*/
 				0x00000000 /*MR3*/
 	>;
  
	 status = "okay";
 };

The optional node st,phy-cal allows to use a calibration result when it is present, for example: 

 &ddr {
...
  	st,phy-cal = <
  		0x40000000 /*DX0DLLCR*/
  		0xFFFFFFFF /*DX0DQTR*/
  		0x3DB02000 /*DX0DQSTR*/
  		0x40000000 /*DX1DLLCR*/
  		0xFFFFFFFF /*DX1DQTR*/
  		0x3DB02000 /*DX1DQSTR*/
  		0x40000000 /*DX2DLLCR*/
  		0xFFFFFFFF /*DX2DQTR*/
  		0x3DB02000 /*DX2DQSTR*/
  		0x40000000 /*DX3DLLCR*/
  		0xFFFFFFFF /*DX3DQTR*/
  		0x3DB02000 /*DX3DQSTR*/
  	>;
...
        };
3.3.1.2. STM32CubeMX configuration file[edit source]

STM32CubeMX generates a .dtsi file with the needed values as defines (named DDR_...), and includes the #Generic DDR dtsi file for STM32MP1 series: as this dtsi file is preprocessed during FSBL compilation, it generates a correct device tree.

For example the file fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi is: 

  / SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  /*
   * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
   * DDR type: DDR3 / DDR3L
   * DDR width: 16bits
   * DDR density: 4Gb
   * System frequency: 533000Khz
   * Relaxed Timing Mode: false
   * Address mapping type: RBC
   *
   * Save Date: 2020.02.20, save Time: 18:45:20
   */
  
  #define DDR_MEM_NAME	"DDR3-DDR3L 16bits 533000kHz"
  #define DDR_MEM_SPEED	533000
  #define DDR_MEM_SIZE	0x20000000
 
  #define DDR_MSTR 0x00041401
  #define DDR_MRCTRL0 0x00000010
  #define DDR_MRCTRL1 0x00000000
  #define DDR_DERATEEN 0x00000000
  #define DDR_DERATEINT 0x00800000
  .....
  #define DDR_DX2DQSTR 0x3DB02000
  #define DDR_DX3GCR 0x0000CE80
  #define DDR_DX3DLLCR 0x40000000
  #define DDR_DX3DQTR 0xFFFFFFFF
  #define DDR_DX3DQSTR 0x3DB02000
  
  #include "stm32mp15-ddr.dtsi"

NB: the calibration values (DXnDLLCR, DXnDQTR, DXnDQSTR, with n in 1...3) are not used when DDR_PHY_CAL_SKIP is not defined, only the built-in calibration is done.

3.3.1.3. Generic DDR dtsi file for STM32MP1 series[edit source]

The dtsi file used with DDR_ defines is

  • stm32mp13-ddr.dtsi[6] for STM32MP13x lines More info.png
  • stm32mp15-ddr.dtsi[7] for STM32MP15x lines More info.png

For example, stm32mp15-ddr.dtsi is: 

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
 */

&ddr {
	st,mem-name = DDR_MEM_NAME;
	st,mem-speed = <DDR_MEM_SPEED>;
	st,mem-size = <DDR_MEM_SIZE>;

	st,ctl-reg = <
		DDR_MSTR
		DDR_MRCTRL0
		DDR_MRCTRL1
		DDR_DERATEEN
		DDR_DERATEINT
		DDR_PWRCTL
		DDR_PWRTMG
		DDR_HWLPCTL
		DDR_RFSHCTL0
		DDR_RFSHCTL3
		DDR_CRCPARCTL0
		DDR_ZQCTL0
		DDR_DFITMG0
		DDR_DFITMG1
		DDR_DFILPCFG0
		DDR_DFIUPD0
		DDR_DFIUPD1
		DDR_DFIUPD2
		DDR_DFIPHYMSTR
		DDR_ODTMAP
		DDR_DBG0
		DDR_DBG1
		DDR_DBGCMD
		DDR_POISONCFG
		DDR_PCCFG
	>;

	st,ctl-timing = <
		DDR_RFSHTMG
		DDR_DRAMTMG0
		DDR_DRAMTMG1
		DDR_DRAMTMG2
		DDR_DRAMTMG3
		DDR_DRAMTMG4
		DDR_DRAMTMG5
		DDR_DRAMTMG6
		DDR_DRAMTMG7
		DDR_DRAMTMG8
		DDR_DRAMTMG14
		DDR_ODTCFG
	>;

	st,ctl-map = <
		DDR_ADDRMAP1
		DDR_ADDRMAP2
		DDR_ADDRMAP3
		DDR_ADDRMAP4
		DDR_ADDRMAP5
		DDR_ADDRMAP6
		DDR_ADDRMAP9
		DDR_ADDRMAP10
		DDR_ADDRMAP11
	>;

	st,ctl-perf = <
		DDR_SCHED
		DDR_SCHED1
		DDR_PERFHPR1
		DDR_PERFLPR1
		DDR_PERFWR1
		DDR_PCFGR_0
		DDR_PCFGW_0
		DDR_PCFGQOS0_0
		DDR_PCFGQOS1_0
		DDR_PCFGWQOS0_0
		DDR_PCFGWQOS1_0
		DDR_PCFGR_1
		DDR_PCFGW_1
		DDR_PCFGQOS0_1
		DDR_PCFGQOS1_1
		DDR_PCFGWQOS0_1
		DDR_PCFGWQOS1_1
	>;

	st,phy-reg = <
		DDR_PGCR
		DDR_ACIOCR
		DDR_DXCCR
		DDR_DSGCR
		DDR_DCR
		DDR_ODTCR
		DDR_ZQ0CR1
		DDR_DX0GCR
		DDR_DX1GCR
		DDR_DX2GCR
		DDR_DX3GCR
	>;

	st,phy-timing = <
		DDR_PTR0
		DDR_PTR1
		DDR_PTR2
		DDR_DTPR0
		DDR_DTPR1
		DDR_DTPR2
		DDR_MR0
		DDR_MR1
		DDR_MR2
		DDR_MR3
	>;

#ifdef DDR_PHY_CAL_SKIP
	st,phy-cal = <
		DDR_DX0DLLCR
		DDR_DX0DQTR
		DDR_DX0DQSTR
		DDR_DX1DLLCR
		DDR_DX1DQTR
		DDR_DX1DQSTR
		DDR_DX2DLLCR
		DDR_DX2DQTR
		DDR_DX2DQSTR
		DDR_DX3DLLCR
		DDR_DX3DQTR
		DDR_DX3DQSTR
	>;
#endif
};

3.3.2. On STM32MP2 series[edit source]

3.3.2.1. Simple example[edit source]

You can add the DDR configuration node with (STM32MP25x lines More info.png example): 

  &ddr {
  	st,mem-name = "DDR4 2x16Gbits 2x16bits 1200MHz";
  	st,mem-speed = <1200000>;
  	st,mem-size = <(0x100000000 >> 32) (0x100000000 & 0xFFFFFFFF)>;
  
  	st,ctl-reg = <
  				0x01040010
  				0x00000030
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00130001
  				0x00000002
  				0x00210010
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00001000
  				0xC0020002
  				0x00010002
  				0x00000D00
  				0x09400103
  				0x00180000
  				0x00100004
  				0x00080460
  				0x00000C0F
  				0x00000000
  				0x0000066F
  				0x01000040
  				0x2000493E
  				0x00000000
  				0x038F8209
  				0x00080303
  				0x07004111
  				0x00000000
  				0xC0300018
  				0x005700B4
  				0x80000000
  				0x00000041
  				0x00000F09
  				0x00000000
  				0x00000001
  				0x80000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  	>;

  	st,ctl-timing = <
  				0x0092014A
  				0x008C0000
  				0x11152815
  				0x0004051E
  				0x0609060D
  				0x0050400C
  				0x0904050A
  				0x06060403
  				0x02020005
  				0x00000202
  				0x0606100B
  				0x0002040A
  				0x001C180A
  				0x4408021C
  				0x0C020010
  				0x1C200004
  				0x000000A0
  				0x00000000
  				0x06000618
  				0x00000001
  	>;

  	st,ctl-map = <
  				0x0000001F
  				0x003F0909
  				0x00000000
  				0x00000000
  				0x00001F1F
  				0x070F0707
  				0x07070707
  				0x00000F07
  				0x00003F08
  				0x07070707
  				0x07070707
  				0x00000007
  	>;

  	st,ctl-perf = <
  				0x80001B0C
  				0x00000000
  				0x04000200
  				0x08000020
  				0x08000400
  				0x00704100
  				0x00004100
  				0x00000000
  				0x0021000C
  				0x01000080
  				0x01100C07
  				0x04000200
  				0x00704100
  				0x00004100
  				0x00000000
  				0x00100007
  				0x01000080
  				0x01100C07
  				0x04000200
  	>;

  	st,phy-basic = <
  				0x00000000
  				0x00000004
  				0x00000000
  				0x00000004
  				0x00000004
  				0x00000000
  				0x00000008
  				0x00000001
  				0x00000001
  				0x00000010
  				0x00000001
  				0x000004B0
  				0x00000000
  				0x00000001
  				0x00000001
  				0x00000000
  				0x00000003
  				0x00000000
  				0x00000000
  	>;

  	st,phy-advanced = <
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000035
  				0x00000028
  				0x00000028
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000001
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000009
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x0000000F
  				0x0000000F
  				0x0000000F
  				0x0000000F
  				0x00000001
  				0x00000000
  				0x00000000
  				0x00000001
  				0x00000000
  				0x00000000
  				0x0000005E
  				0x0000031F
  	>;

  	st,phy-mr = <
  				0x00000940
  				0x00000103
  				0x00000018
  				0x00000000
  				0x00000008
  				0x00000460
  				0x00000C0F
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  	>;

  	st,phy-swizzle = <
  				0x0000000C
  				0x00000005
  				0x00000013
  				0x0000001A
  				0x00000009
  				0x00000003
  				0x00000001
  				0x00000019
  				0x00000007
  				0x00000004
  				0x0000000A
  				0x0000000D
  				0x00000014
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000006
  				0x0000000B
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000008
  				0x00000002
  				0x00000018
  				0x1A13050C
  				0x19010309
  				0x0D0A0407
  				0x00000014
  				0x000B0600
  				0x02080000
  				0x00000018
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  				0x00000000
  	>;

	 status = "okay";
 };
3.3.2.2. STM32CubeMX configuration file[edit source]

STM32CubeMX generates a .dtsi file with the needed values as defines (named DDR_...), and includes the #Generic DDR dtsi file for STM32MP2 series: as this dtsi file is preprocessed during FSBL compilation, it generates a correct device tree.

For example the file fdts/stm32mp25-ddr4-2x16Gbits-2x16bits-1200MHz.dtsi is: 

/*
 * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
 *
 * SPDX-License-Identifier:	GPL-2.0-or-later	BSD-3-Clause
 *
 */
  /*
   * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
   * DDR type: DDR4
   * DDR width: 32 bits
   * DDR density: 32Gb
   * System frequency: 1200000kHz
   * Address mapping type: RBC
   *
   * Save Date: 2023.10.13, save Time: 16:12:09
   */
  
  #define DDR_MEM_NAME "DDR4 32 bits 933000kHz"
  #define DDR_MEM_SPEED 933000
  #define DDR_MEM_SIZE 0x100000000
  
  #define DDR_MSTR 0x01040010
  #define DDR_MRCTRL0 0x00000030
  #define DDR_MRCTRL1 0x00000000
  #define DDR_MRCTRL2 0x00000000
  #define DDR_DERATEEN 0x00000000
  #define DDR_DERATEINT 0x00000000
  #define DDR_DERATECTL 0x00000000
  #define DDR_PWRCTL 0x00000000
  #define DDR_PWRTMG 0x00130001
  #define DDR_HWLPCTL 0x00000002
  #define DDR_RFSHCTL0 0x00210010
  #define DDR_RFSHCTL1 0x00000000
  #define DDR_RFSHCTL3 0x00000000
  #define DDR_RFSHTMG 0x0092014A
  #define DDR_RFSHTMG1 0x008C0000
  #define DDR_CRCPARCTL0 0x00000000
  #define DDR_CRCPARCTL1 0x00001000
  #define DDR_INIT0 0xC0020002
  #define DDR_INIT1 0x00010002
  #define DDR_INIT2 0x00000D00
  #define DDR_INIT3 0x09400103
  #define DDR_INIT4 0x00180000
  #define DDR_INIT5 0x00100004
  #define DDR_INIT6 0x00080460
  #define DDR_INIT7 0x0000080F
  #define DDR_DIMMCTL 0x00000000
  #define DDR_RANKCTL 0x0000066F
  #define DDR_RANKCTL1 0x0000000D
  #define DDR_DRAMTMG0 0x11042809
  #define DDR_DRAMTMG1 0x00040513
  #define DDR_DRAMTMG2 0x0609060D
  #define DDR_DRAMTMG3 0x0050400C
  #define DDR_DRAMTMG4 0x09151E0B
  #define DDR_DRAMTMG5 0x06060403
  #define DDR_DRAMTMG6 0x02020005
  #define DDR_DRAMTMG7 0x00000202
  #define DDR_DRAMTMG8 0x06060C0B
  #define DDR_DRAMTMG9 0x0002090A
  #define DDR_DRAMTMG10 0x001C180A
  #define DDR_DRAMTMG11 0x4408021C
  #define DDR_DRAMTMG12 0x0C020010
  #define DDR_DRAMTMG13 0x1C200004
  #define DDR_DRAMTMG14 0x000000A0
  #define DDR_DRAMTMG15 0x00000000
  #define DDR_ZQCTL0 0x01000040
  #define DDR_ZQCTL1 0x2000492E
  #define DDR_ZQCTL2 0x00000000
  #define DDR_DFITMG0 0x038F8209
  #define DDR_DFITMG1 0x00080303
  #define DDR_DFILPCFG0 0x07004111
  #define DDR_DFILPCFG1 0x00000000
  #define DDR_DFIUPD0 0xC0300018
  #define DDR_DFIUPD1 0x005700B4
  #define DDR_DFIUPD2 0x80000000
  #define DDR_DFIMISC 0x00000041
  #define DDR_DFITMG2 0x00000F09
  #define DDR_DFITMG3 0x00000000
  #define DDR_DBICTL 0x00000001
  #define DDR_DFIPHYMSTR 0x80000000
  #define DDR_ADDRMAP0 0x0000001F
  #define DDR_ADDRMAP1 0x003F0909
  #define DDR_ADDRMAP2 0x00000000
  #define DDR_ADDRMAP3 0x00000000
  #define DDR_ADDRMAP4 0x00001F1F
  #define DDR_ADDRMAP5 0x070F0707
  #define DDR_ADDRMAP6 0x07070707
  #define DDR_ADDRMAP7 0x00000F07
  #define DDR_ADDRMAP8 0x00003F08
  #define DDR_ADDRMAP9 0x07070707
  #define DDR_ADDRMAP10 0x07070707
  #define DDR_ADDRMAP11 0x00000007
  #define DDR_ODTCFG 0x06000618
  #define DDR_ODTMAP 0x00000001
  #define DDR_SCHED 0x80001B0C
  #define DDR_SCHED1 0x00000000
  #define DDR_PERFHPR1 0x04000200
  #define DDR_PERFLPR1 0x08000020
  #define DDR_PERFWR1 0x08000400
  #define DDR_SCHED3 0x04040208
  #define DDR_SCHED4 0x08400810
  #define DDR_DBG0 0x00000000
  #define DDR_DBG1 0x00000000
  #define DDR_DBGCMD 0x00000000
  #define DDR_SWCTL 0x00000000
  #define DDR_SWCTLSTATIC 0x00000000
  #define DDR_POISONCFG 0x00000000
  #define DDR_PCCFG 0x00000000
  #define DDR_PCFGR_0 0x00704100
  #define DDR_PCFGW_0 0x00004100
  #define DDR_PCTRL_0 0x00000000
  #define DDR_PCFGQOS0_0 0x0021000C
  #define DDR_PCFGQOS1_0 0x01000080
  #define DDR_PCFGWQOS0_0 0x01100C07
  #define DDR_PCFGWQOS1_0 0x04000200
  #define DDR_PCFGR_1 0x00704100
  #define DDR_PCFGW_1 0x00004100
  #define DDR_PCTRL_1 0x00000000
  #define DDR_PCFGQOS0_1 0x00100007
  #define DDR_PCFGQOS1_1 0x01000080
  #define DDR_PCFGWQOS0_1 0x01100C07
  #define DDR_PCFGWQOS1_1 0x04000200
  
  #define DDR_UIB_DRAMTYPE 0x00000000
  #define DDR_UIB_DIMMTYPE 0x00000004
  #define DDR_UIB_LP4XMODE 0x00000000
  #define DDR_UIB_NUMDBYTE 0x00000004
  #define DDR_UIB_NUMACTIVEDBYTEDFI0 0x00000004
  #define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000000
  #define DDR_UIB_NUMANIB 0x00000008
  #define DDR_UIB_NUMRANK_DFI0 0x00000001
  #define DDR_UIB_NUMRANK_DFI1 0x00000001
  #define DDR_UIB_DRAMDATAWIDTH 0x00000010
  #define DDR_UIB_NUMPSTATES 0x00000001
  #define DDR_UIB_FREQUENCY_0 0x000004AF
  #define DDR_UIB_PLLBYPASS_0 0x00000000
  #define DDR_UIB_DFIFREQRATIO_0 0x00000001
  #define DDR_UIB_DFI1EXISTS 0x00000001
  #define DDR_UIB_TRAIN2D 0x00000000
  #define DDR_UIB_HARDMACROVER 0x00000003
  #define DDR_UIB_READDBIENABLE_0 0x00000000
  #define DDR_UIB_DFIMODE 0x00000000
  
  #define DDR_UIA_LP4RXPREAMBLEMODE_0 0x00000000
  #define DDR_UIA_LP4POSTAMBLEEXT_0 0x00000000
  #define DDR_UIA_D4RXPREAMBLELENGTH_0 0x00000000
  #define DDR_UIA_D4TXPREAMBLELENGTH_0 0x00000000
  #define DDR_UIA_EXTCALRESVAL 0x00000000
  #define DDR_UIA_IS2TTIMING_0 0x00000000
  #define DDR_UIA_ODTIMPEDANCE_0 0x00000035
  #define DDR_UIA_TXIMPEDANCE_0 0x00000028
  #define DDR_UIA_ATXIMPEDANCE 0x00000028
  #define DDR_UIA_MEMALERTEN 0x00000000
  #define DDR_UIA_MEMALERTPUIMP 0x00000000
  #define DDR_UIA_MEMALERTVREFLEVEL 0x00000000
  #define DDR_UIA_MEMALERTSYNCBYPASS 0x00000000
  #define DDR_UIA_DISDYNADRTRI_0 0x00000001
  #define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x00000000
  #define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000000
  #define DDR_UIA_WDQSEXT 0x00000000
  #define DDR_UIA_CALINTERVAL 0x00000009
  #define DDR_UIA_CALONCE 0x00000000
  #define DDR_UIA_LP4RL_0 0x00000000
  #define DDR_UIA_LP4WL_0 0x00000000
  #define DDR_UIA_LP4WLS_0 0x00000000
  #define DDR_UIA_LP4DBIRD_0 0x00000000
  #define DDR_UIA_LP4DBIWR_0 0x00000000
  #define DDR_UIA_LP4NWR_0 0x00000000
  #define DDR_UIA_LP4LOWPOWERDRV 0x00000000
  #define DDR_UIA_DRAMBYTESWAP 0x00000000
  #define DDR_UIA_RXENBACKOFF 0x00000000
  #define DDR_UIA_TRAINSEQUENCECTRL 0x00000000
  #define DDR_UIA_SNPSUMCTLOPT 0x00000000
  #define DDR_UIA_SNPSUMCTLF0RC5X_0 0x00000000
  #define DDR_UIA_TXSLEWRISEDQ_0 0x0000000F
  #define DDR_UIA_TXSLEWFALLDQ_0 0x0000000F
  #define DDR_UIA_TXSLEWRISEAC 0x0000000F
  #define DDR_UIA_TXSLEWFALLAC 0x0000000F
  #define DDR_UIA_DISABLERETRAINING 0x00000001
  #define DDR_UIA_DISABLEPHYUPDATE 0x00000000
  #define DDR_UIA_ENABLEHIGHCLKSKEWFIX 0x00000000
  #define DDR_UIA_DISABLEUNUSEDADDRLNS 0x00000001
  #define DDR_UIA_PHYINITSEQUENCENUM 0x00000000
  #define DDR_UIA_ENABLEDFICSPOLARITYFIX 0x00000000
  #define DDR_UIA_PHYVREF 0x0000005E
  #define DDR_UIA_SEQUENCECTRL_0 0x0000031F
  
  #define DDR_UIM_MR0_0 0x00000940
  #define DDR_UIM_MR1_0 0x00000103
  #define DDR_UIM_MR2_0 0x00000018
  #define DDR_UIM_MR3_0 0x00000000
  #define DDR_UIM_MR4_0 0x00000008
  #define DDR_UIM_MR5_0 0x00000460
  #define DDR_UIM_MR6_0 0x0000080F
  #define DDR_UIM_MR11_0 0x00000000
  #define DDR_UIM_MR12_0 0x00000000
  #define DDR_UIM_MR13_0 0x00000000
  #define DDR_UIM_MR14_0 0x00000000
  #define DDR_UIM_MR22_0 0x00000000
  
  #define DDR_UIS_SWIZZLE_0 0x0000000C
  #define DDR_UIS_SWIZZLE_1 0x00000005
  #define DDR_UIS_SWIZZLE_2 0x00000013
  #define DDR_UIS_SWIZZLE_3 0x0000001A
  #define DDR_UIS_SWIZZLE_4 0x00000009
  #define DDR_UIS_SWIZZLE_5 0x00000003
  #define DDR_UIS_SWIZZLE_6 0x00000001
  #define DDR_UIS_SWIZZLE_7 0x00000019
  #define DDR_UIS_SWIZZLE_8 0x00000007
  #define DDR_UIS_SWIZZLE_9 0x00000004
  #define DDR_UIS_SWIZZLE_10 0x0000000A
  #define DDR_UIS_SWIZZLE_11 0x0000000D
  #define DDR_UIS_SWIZZLE_12 0x00000014
  #define DDR_UIS_SWIZZLE_13 0x00000000
  #define DDR_UIS_SWIZZLE_14 0x00000000
  #define DDR_UIS_SWIZZLE_15 0x00000000
  #define DDR_UIS_SWIZZLE_16 0x00000000
  #define DDR_UIS_SWIZZLE_17 0x00000000
  #define DDR_UIS_SWIZZLE_18 0x00000006
  #define DDR_UIS_SWIZZLE_19 0x0000000B
  #define DDR_UIS_SWIZZLE_20 0x00000000
  #define DDR_UIS_SWIZZLE_21 0x00000000
  #define DDR_UIS_SWIZZLE_22 0x00000000
  #define DDR_UIS_SWIZZLE_23 0x00000008
  #define DDR_UIS_SWIZZLE_24 0x00000002
  #define DDR_UIS_SWIZZLE_25 0x00000018
  #define DDR_UIS_SWIZZLE_26 0x1A13050C
  #define DDR_UIS_SWIZZLE_27 0x19010309
  #define DDR_UIS_SWIZZLE_28 0x0D0A0407
  #define DDR_UIS_SWIZZLE_29 0x00000014
  #define DDR_UIS_SWIZZLE_30 0x000B0600
  #define DDR_UIS_SWIZZLE_31 0x02080000
  #define DDR_UIS_SWIZZLE_32 0x00000018
  #define DDR_UIS_SWIZZLE_33 0x00000000
  #define DDR_UIS_SWIZZLE_34 0x00000000
  #define DDR_UIS_SWIZZLE_35 0x00000000
  #define DDR_UIS_SWIZZLE_36 0x00000000
  #define DDR_UIS_SWIZZLE_37 0x00000000
  #define DDR_UIS_SWIZZLE_38 0x00000000
  #define DDR_UIS_SWIZZLE_39 0x00000000
  #define DDR_UIS_SWIZZLE_40 0x00000000
  #define DDR_UIS_SWIZZLE_41 0x00000000
  #define DDR_UIS_SWIZZLE_42 0x00000000
  #define DDR_UIS_SWIZZLE_43 0x00000000
  
  #include "stm32mp25-ddr.dtsi"
3.3.2.3. Generic DDR dtsi file for STM32MP2 series[edit source]

The dtsi file used with DDR_ defines is

  • stm32mp25-ddr.dtsi[8] for STM32MP25x lines More info.png

For example, stm32mp25-ddr.dtsi is: 

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
 */

&ddr{
	st,mem-name = DDR_MEM_NAME;
	st,mem-speed = <DDR_MEM_SPEED>;
	st,mem-size = <(DDR_MEM_SIZE >> 32) (DDR_MEM_SIZE & 0xFFFFFFFF)>;

	st,ctl-reg = <
		DDR_MSTR
		DDR_MRCTRL0
		DDR_MRCTRL1
		DDR_MRCTRL2
		DDR_DERATEEN
		DDR_DERATEINT
		DDR_DERATECTL
		DDR_PWRCTL
		DDR_PWRTMG
		DDR_HWLPCTL
		DDR_RFSHCTL0
		DDR_RFSHCTL1
		DDR_RFSHCTL3
		DDR_CRCPARCTL0
		DDR_CRCPARCTL1
		DDR_INIT0
		DDR_INIT1
		DDR_INIT2
		DDR_INIT3
		DDR_INIT4
		DDR_INIT5
		DDR_INIT6
		DDR_INIT7
		DDR_DIMMCTL
		DDR_RANKCTL
		DDR_RANKCTL1
		DDR_ZQCTL0
		DDR_ZQCTL1
		DDR_ZQCTL2
		DDR_DFITMG0
		DDR_DFITMG1
		DDR_DFILPCFG0
		DDR_DFILPCFG1
		DDR_DFIUPD0
		DDR_DFIUPD1
		DDR_DFIUPD2
		DDR_DFIMISC
		DDR_DFITMG2
		DDR_DFITMG3
		DDR_DBICTL
		DDR_DFIPHYMSTR
		DDR_DBG0
		DDR_DBG1
		DDR_DBGCMD
		DDR_SWCTL
		DDR_SWCTLSTATIC
		DDR_POISONCFG
		DDR_PCCFG
	>;

	st,ctl-timing = <
		DDR_RFSHTMG
		DDR_RFSHTMG1
		DDR_DRAMTMG0
		DDR_DRAMTMG1
		DDR_DRAMTMG2
		DDR_DRAMTMG3
		DDR_DRAMTMG4
		DDR_DRAMTMG5
		DDR_DRAMTMG6
		DDR_DRAMTMG7
		DDR_DRAMTMG8
		DDR_DRAMTMG9
		DDR_DRAMTMG10
		DDR_DRAMTMG11
		DDR_DRAMTMG12
		DDR_DRAMTMG13
		DDR_DRAMTMG14
		DDR_DRAMTMG15
		DDR_ODTCFG
		DDR_ODTMAP
	>;

	st,ctl-map = <
		DDR_ADDRMAP0
		DDR_ADDRMAP1
		DDR_ADDRMAP2
		DDR_ADDRMAP3
		DDR_ADDRMAP4
		DDR_ADDRMAP5
		DDR_ADDRMAP6
		DDR_ADDRMAP7
		DDR_ADDRMAP8
		DDR_ADDRMAP9
		DDR_ADDRMAP10
		DDR_ADDRMAP11
	>;

	st,ctl-perf = <
		DDR_SCHED
		DDR_SCHED1
		DDR_PERFHPR1
		DDR_PERFLPR1
		DDR_PERFWR1
		DDR_SCHED3
		DDR_SCHED4
		DDR_PCFGR_0
		DDR_PCFGW_0
		DDR_PCTRL_0
		DDR_PCFGQOS0_0
		DDR_PCFGQOS1_0
		DDR_PCFGWQOS0_0
		DDR_PCFGWQOS1_0
		DDR_PCFGR_1
		DDR_PCFGW_1
		DDR_PCTRL_1
		DDR_PCFGQOS0_1
		DDR_PCFGQOS1_1
		DDR_PCFGWQOS0_1
		DDR_PCFGWQOS1_1
	>;

	st,phy-basic = <
		DDR_UIB_DRAMTYPE
		DDR_UIB_DIMMTYPE
		DDR_UIB_LP4XMODE
		DDR_UIB_NUMDBYTE
		DDR_UIB_NUMACTIVEDBYTEDFI0
		DDR_UIB_NUMACTIVEDBYTEDFI1
		DDR_UIB_NUMANIB
		DDR_UIB_NUMRANK_DFI0
		DDR_UIB_NUMRANK_DFI1
		DDR_UIB_DRAMDATAWIDTH
		DDR_UIB_NUMPSTATES
		DDR_UIB_FREQUENCY_0
		DDR_UIB_PLLBYPASS_0
		DDR_UIB_DFIFREQRATIO_0
		DDR_UIB_DFI1EXISTS
		DDR_UIB_TRAIN2D
		DDR_UIB_HARDMACROVER
		DDR_UIB_READDBIENABLE_0
		DDR_UIB_DFIMODE
	>;

	st,phy-advanced = <
		DDR_UIA_LP4RXPREAMBLEMODE_0
		DDR_UIA_LP4POSTAMBLEEXT_0
		DDR_UIA_D4RXPREAMBLELENGTH_0
		DDR_UIA_D4TXPREAMBLELENGTH_0
		DDR_UIA_EXTCALRESVAL
		DDR_UIA_IS2TTIMING_0
		DDR_UIA_ODTIMPEDANCE_0
		DDR_UIA_TXIMPEDANCE_0
		DDR_UIA_ATXIMPEDANCE
		DDR_UIA_MEMALERTEN
		DDR_UIA_MEMALERTPUIMP
		DDR_UIA_MEMALERTVREFLEVEL
		DDR_UIA_MEMALERTSYNCBYPASS
		DDR_UIA_DISDYNADRTRI_0
		DDR_UIA_PHYMSTRTRAININTERVAL_0
		DDR_UIA_PHYMSTRMAXREQTOACK_0
		DDR_UIA_WDQSEXT
		DDR_UIA_CALINTERVAL
		DDR_UIA_CALONCE
		DDR_UIA_LP4RL_0
		DDR_UIA_LP4WL_0
		DDR_UIA_LP4WLS_0
		DDR_UIA_LP4DBIRD_0
		DDR_UIA_LP4DBIWR_0
		DDR_UIA_LP4NWR_0
		DDR_UIA_LP4LOWPOWERDRV
		DDR_UIA_DRAMBYTESWAP
		DDR_UIA_RXENBACKOFF
		DDR_UIA_TRAINSEQUENCECTRL
		DDR_UIA_SNPSUMCTLOPT
		DDR_UIA_SNPSUMCTLF0RC5X_0
		DDR_UIA_TXSLEWRISEDQ_0
		DDR_UIA_TXSLEWFALLDQ_0
		DDR_UIA_TXSLEWRISEAC
		DDR_UIA_TXSLEWFALLAC
		DDR_UIA_DISABLERETRAINING
		DDR_UIA_DISABLEPHYUPDATE
		DDR_UIA_ENABLEHIGHCLKSKEWFIX
		DDR_UIA_DISABLEUNUSEDADDRLNS
		DDR_UIA_PHYINITSEQUENCENUM
		DDR_UIA_ENABLEDFICSPOLARITYFIX
		DDR_UIA_PHYVREF
		DDR_UIA_SEQUENCECTRL_0
	>;

	st,phy-mr = <
		DDR_UIM_MR0_0
		DDR_UIM_MR1_0
		DDR_UIM_MR2_0
		DDR_UIM_MR3_0
		DDR_UIM_MR4_0
		DDR_UIM_MR5_0
		DDR_UIM_MR6_0
		DDR_UIM_MR11_0
		DDR_UIM_MR12_0
		DDR_UIM_MR13_0
		DDR_UIM_MR14_0
		DDR_UIM_MR22_0
	>;

	st,phy-swizzle = <
		DDR_UIS_SWIZZLE_0
		DDR_UIS_SWIZZLE_1
		DDR_UIS_SWIZZLE_2
		DDR_UIS_SWIZZLE_3
		DDR_UIS_SWIZZLE_4
		DDR_UIS_SWIZZLE_5
		DDR_UIS_SWIZZLE_6
		DDR_UIS_SWIZZLE_7
		DDR_UIS_SWIZZLE_8
		DDR_UIS_SWIZZLE_9
		DDR_UIS_SWIZZLE_10
		DDR_UIS_SWIZZLE_11
		DDR_UIS_SWIZZLE_12
		DDR_UIS_SWIZZLE_13
		DDR_UIS_SWIZZLE_14
		DDR_UIS_SWIZZLE_15
		DDR_UIS_SWIZZLE_16
		DDR_UIS_SWIZZLE_17
		DDR_UIS_SWIZZLE_18
		DDR_UIS_SWIZZLE_19
		DDR_UIS_SWIZZLE_20
		DDR_UIS_SWIZZLE_21
		DDR_UIS_SWIZZLE_22
		DDR_UIS_SWIZZLE_23
		DDR_UIS_SWIZZLE_24
		DDR_UIS_SWIZZLE_25
		DDR_UIS_SWIZZLE_26
		DDR_UIS_SWIZZLE_27
		DDR_UIS_SWIZZLE_28
		DDR_UIS_SWIZZLE_29
		DDR_UIS_SWIZZLE_30
		DDR_UIS_SWIZZLE_31
		DDR_UIS_SWIZZLE_32
		DDR_UIS_SWIZZLE_33
		DDR_UIS_SWIZZLE_34
		DDR_UIS_SWIZZLE_35
		DDR_UIS_SWIZZLE_36
		DDR_UIS_SWIZZLE_37
		DDR_UIS_SWIZZLE_38
		DDR_UIS_SWIZZLE_39
		DDR_UIS_SWIZZLE_40
		DDR_UIS_SWIZZLE_41
		DDR_UIS_SWIZZLE_42
		DDR_UIS_SWIZZLE_43
	>;
};

4. How to configure the DT using STM32CubeMX[edit source]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.

The STM32CubeMX supports all the defines described in the above DT bindings documentation paragraph with a generated included file "stm32mp15-mx.dtsi"; it is included in the mx dts file before the #Generic DDR dtsi file . Refer to the STM32CubeMX user manual and the dedicated application note[5] for further information.


If you want to use the STM32CubeMX DDR Tuning Tool calibration result, add in the generated files "stm32mp15-mx.dtsi" the line: 

  #define DDR_PHY_CAL_SKIP

5. References[edit source]

Please refer to the following links for additional information:

  1. ↑ docs/devicetree/bindings/memory-controllers/st,stm32mp1-ddr.txt TF-A DDR binding information file
  2. ↑ docs/devicetree/bindings/memory-controllers/st,stm32mp2-ddr.txt TF-A DDR binding information file
  3. ↑ stm32mp131.dtsi (for TF-A)
  4. ↑ stm32mp151.dtsi (for TF-A)
  5. ↑ 5.0 5.1 AN5168 - DDR configuration on STM32MP1 series MPU
  6. ↑ fdts/stm32mp13-ddr.dtsi (for TF-A): STM32MP13x DDR device tree file
  7. ↑ fdts/stm32mp15-ddr.dtsi (for TF-A): STM32MP15x DDR device tree file
  8. ↑ fdts/stm32mp25-ddr.dtsi (for TF-A): STM32MP25x DDR device tree file



Doubledata rate (memory domain)

Physical layer protocol

First stage boot loader

Trusted firmware for Arm® Cortex®-A

Device tree

Second stage boot loader

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