1. Article purpose[edit source]
The purpose of this article is to explain how to configure the OCTOSPI I/O manager using the device tree mechanism, relying on the bindings documentation, that is the description of the required and optional device-tree properties.
The peripheral can be assigned to different contexts/software components, depending on the final product needs. Refer to How to assign an internal peripheral to an execution context article for guidelines on this configuration.
2. DT bindings documentation[edit source]
The device tree binding documents are stored either in the given applicable components listed below, or in the Linux kernel repository:
- TF-A BL2, U-Boot, OP-TEE, Linux® OS:
- OCTOSPI I/O manager device tree bindings: Documentation/devicetree/bindings/misc/st,stm32-omm.yaml .
3. DT configuration[edit source]
This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device-tree file organization.
STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.
The OCTOSPI I/O manager is a low-level interface that enables OCTOSPI pin assignment and multiplex of single/dual/quad/octal SPI interfaces over the same bus.
OCTOSPI I/O manager main features :
- Supports up to two single/dual/quad/octal SPI interfaces
- Supports up to two ports for pin assignment
3.1. DT configuration (STM32 level)[edit source]
The OCTOSPI I/O manager node is located in the device tree file for the software components, supporting the peripheral and listed in the above DT bindings documentation paragraph.
3.2. DT configuration (board level)[edit source]
The objective of this chapter is to explain how to enable and configure the OCTOSPI I/O manager DT nodes for a board.
Peripheral configuration should be done in specific board device tree files (board dts file and pinctrl dtsi file).
&ommanager {
memory-region = <&mm_ospi1>;
memory-region-names = "mm_ospi1"; Comments
pinctrl-names = "default", "sleep"; --> For pinctrl configuration, please refer to Pinctrl device tree configuration
pinctrl-0 = <&ospi1_clk_test_pins_b --> pinctrl configuration on OSPI1
&ospi1_io03_test_pins_a
&ospi1_cs0_test_pins_b
&ospi1_cs1_test_pins_b;
pinctrl-1 = <&ospi1_clk_sleep_test_pins_a
&ospi1_io03_sleep_test_pins_a
&ospi1_cs0_sleep_test_pins_a
&ospi1_cs1_sleep_test_pins_a>;
status = "okay"; --> Enable the OCTOSPI I/O manager node
spi@40430000 {
#address-cells = <1>;
#size-cells = <0>;
memory-region = <&mm_ospi1>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <84000000>;
};
};
};
3.3. DT configuration example[edit source]
The below example shows how to configure the OCTOSPI I/O manager peripheral when 2 SPI-NOR Flash memories are connected on OSPI1 port and 2 SPI-NAND Flash memories connected on OSPI2 port.
&ommanager {
memory-region = <&mm_ospi1>, <&mm_ospi2>;
memory-region-names = "mm_ospi1", "mm_ospi2";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ospi1_clk_test_pins_b --> pinctrl configuration for OSPI1
&ospi1_io03_test_pins_a
&ospi1_cs0_test_pins_b
&ospi1_cs1_test_pins_b
&ospi2_clk_test_pins_b --> pinctrl configuration for OSPI2
&ospi2_io03_test_pins_b
&ospi2_cs0_test_pins_b
&ospi2_cs1_test_pins_b>;
pinctrl-1 = <&ospi1_clk_sleep_test_pins_a
&ospi1_io03_sleep_test_pins_a
&ospi1_cs0_sleep_test_pins_a
&ospi1_cs1_sleep_test_pins_a
&ospi2_clk_sleep_test_pins_a
&ospi2_io03_sleep_test_pins_a
&ospi2_cs0_sleep_test_pins_a
&ospi2_cs1_sleep_test_pins_a>;
status = "okay";
spi@40430000 { --> OSPI1 instance
#address-cells = <1>;
#size-cells = <0>;
memory-region = <&mm_ospi1>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <84000000>;
};
flash1: flash@1 {
compatible = "jedec,spi-nor";
reg = <1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <84000000>;
};
};
spi@40440000 { --> OSPI2 instance
#address-cells = <1>;
#size-cells = <0>;
memory-region = <&mm_ospi2>;
status = "okay";
flash2: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <133000000>;
};
flash3: flash@1 {
compatible = "spi-nand";
reg = <1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <133000000>;
};
};
};
The below example shows how to configure the OCTOSPI I/O manager peripheral when 1 HyperFlash memory is connected on OSPI1 port.
&ommanager {
memory-region = <&mm_ospi1>;
memory-region-names = "mm_ospi1";
ranges = <0 0 0x40430000 0x400>,
<1 0 0x40440000 0x400>,
<2 0 0x60000000 0x4000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ospi1_clk_test_pins_b
&ospi1_io03_test_pins_a
&ospi1_io47_test_pins_b
&ospi1_cs0_test_pins_b
&ospi1_dqs_test_pins_a>;
pinctrl-1 = <&ospi1_clk_sleep_test_pins_a
&ospi1_io03_sleep_test_pins_a
&ospi1_io47_sleep_test_pins_a
&ospi1_cs0_sleep_test_pins_a
&ospi1_dqs_sleep_test_pins_a>;
status = "okay";
memory-controller@40430000 {
compatible = "st,stm32mp25-omi";
reg = <0 0 0x400>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
st,syscfg-dlyb = <&syscfg 0x1000>;
clocks = <&scmi_clk CK_SCMI_OSPI1>;
resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>;
feature-domains = <&rifsc STM32MP25_RIFSC_OCTOSPI1_ID>;
#address-cells = <2>;
#size-cells = <1>;
memory-region = <&mm_ospi1>;
ranges;
dmas = <&hpdma 2 0x42 0x00003013 0x0>;
dma-names = "rx";
status = "okay";
flash0: flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x2 0x0 0x4000000>;
st,max-frequency = <100000000>;
st,tacc-ns = <96>;
st,wzl;
};
};
};
4. How to configure the DT using STM32CubeMX[edit source]
The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
STM32CubeMX may not support all the properties described in DT binding files listed in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties, and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.
5. References[edit source]
Refer to the following links for additional information: