This section gives an overview of OP-TEE core drivers (UPPERCASE in the figure) implemented for the STM32MP13 support, with their respective software frameworks (lowercase in the figure).
It is running in Cortex-A7 secure context (EL1S execution level).
Due to Armv7-A architecture, It also runs a dedicated secure monitor which is running in Cortex-A7 EL3 and which is providing Cortex-A7 cluster low power functionalities via PSCI interface.
OP-TEE is in charge of:
- System resources management:
- Internal and external regulators
- Clock tree (PLLs and Root clocks)
- System peripheral clock gating
- Oscillators calibration
- Firewall configuration and dynamic management
- Wakeup pins
- Secure services
- Cryptography via Global Platform (GP) API
- PKCS#11
- Trusted UI
- stMM for secure UEFI
- fTPM (firmware TPM) for TPM emulation
- OTP for provisioning
- SecCopro for secure coprocessor management
STM32MP15x lines 
offers two flavors:
- A default OP-TEE running in DDR that only support system resource management.
- A complete OP-TEE running in internal memory including support of security features.
The configuration is detailed in the STM32MPU_OP-TEE_configuration#STM32MP15x_lines.
Like mentioned STM32 MPU OP-TEE overview, the different features can be independently activated according to customer needs.
The following figure provides an overview of STM32MP15x lines OP-TEE.
The components are grouped per functional domains.
Each OP-TEE framework is further described in OP-TEE secure OS category articles.
Each STM32 MPU peripheral is introduced in peripherals overview articles.
Both those sections are reusing the same functional domain split.
The color code, explained in the legend, allows to see the code origin for each component.
