1. Article purpose[edit source]
The purpose of this article is to:
- briefly introduce the OCTOSPI peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit source]
The OCTOSPI peripheral interfaces the processor with serial NOR, serial NAND and HyperFlash flash memories.
It supports:
- Single, Dual-, Quad- or Octal-SPI flash memories
- HyperFlash memories
- Dual data rate
- Memory-mapped modes for read access.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit source]
3.1.1. On STM32MP2 series[edit source]
Click on 
to expand or collapse the legend...
- ☐ means that the peripheral can be assigned to the given boot time context.
- ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 non-secure (U-Boot) | |||
| Mass storage | OCTOSPI | OCTOSPI1 | ☐ | ☐ | ☐ | |
| OCTOSPI2 | ☐ | ☐ | ||||
3.2. Runtime assignment[edit source]
3.2.1. On STM32MP25x lines 
[edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 non-secure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 non-secure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| Mass storage | OCTOSPI | OCTOSPI1 | ⬚OP-TEE | ☐ | ☐ | ☐ | OP-TEE need to access OCTOSPI1 at boot time to set OSPIM mode | |
| OCTOSPI2 | ⬚OP-TEE | ☐ | ☐ | ☐ | OP-TEE need to access OCTOSPI2 at boot time to set OSPIM mode | |||
4. Software frameworks and drivers[edit source]
Below are listed the software frameworks and drivers managing the OCTOSPI peripheral for the embedded software components listed in the above tables.
- Linux®: MTD framework and driver (drivers/spi/spi-stm32-ospi.c )
- STM32Cube: OCTOSPI HAL driver and header file of OCTOSPI HAL module
- TF-A BL2: MTD frameworks (drivers/mtd/ ) and driver (drivers/st/spi/stm32_ospi.c )
- U-Boot: MTD frameworks (drivers/mtd/ ) and drivers (drivers/spi/stm32_ospi.c )
5. How to assign and configure the peripheral[edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral by generating:
- partial device trees (pin control and clock tree) for the OpenSTLinux software components,
- HAL initialization code for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
For Linux kernel configuration, refer to OCTOSPI device tree configuration.
6. References[edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 