RISAF device tree configuration

Applicable for

1. Article purpose[edit source]

The purpose of this article is to explain how to configure the RISAF peripheral using the device tree mechanism, relying on the bindings documentation, that is the description of the required and optional device-tree properties.

The peripheral configuration can only be done by the CPU running in TDCID mode.

2. DT bindings documentation[edit source]

The RISAF declare a number of memory regions thanks to the "memory-region" property. Those region then hold the RIF configuration in the "st,protreg" property.

The device tree binding documents are stored either in the given applicable components listed below:

OP-TEE:
- Reserved-memory device tree bindings: Memory region and its RIF configuration
- RISAF device tree bindings RISAF bindings

3. DT configuration[edit source]

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device-tree file organization.

STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.

RISAF is used to assign memory regions and subregions to one or more security domains (secure, privilege, compartment). The definition of these regions/subregions resides in the board-resmem device tree file and their secure configuration resides in the board-rif device tree file. Both are fully customizable.

Information

Note: For now, only the region definition is supported.

3.1. DT configuration (STM32/SoC level)[edit source]

The RISAF node is located in the device tree file for the software components, supporting the peripheral and listed in the above DT bindings documentation paragraph.

Warning

This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

The RISAF nodes are defined at SoC device file level as:

  //Comments
 
 risaf1: risaf@420a0000 {
       compatible = "st,stm32mp25-risaf";
       reg = <0x420a0000 0x1000>;
       clocks = <&rcc CK_BUS_BKPSRAM>;
       st,mem-map = <0x0 0x42000000 0x0 0x2000>;      //Memory range covered by the RISAF (8KBytes BKPSRAM)
 };
 ...
 risaf4: risaf@420d0000 {
       compatible = "st,stm32mp25-risaf-enc";      //Indicates that the RISAF instance supports encryption
       reg = <0x420d0000 0x1000>;
       clocks = <&rcc CK_BUS_RISAF4>;
       st,mem-map = <0x0 0x80000000 0x1 0x00000000>;      //Memory range covered by the RISAF (4GBytes (DDR))
 };

3.2. DT configuration (board level)[edit source]

The objective of this chapter is to explain how to enable and configure the RISAF DT nodes for a board.

Memory regions and security configurations should be done in specific board device tree files (board-resmem (regions) board-rif (secure configuration))

3.2.1. DT configuration (board level) - board device tree[edit source]

Peripheral configuration should be done in specific board device tree files (board dts file and pinctrl dtsi file).

If pins of the internal peripheral need to be configured, then links to Pinctrl device tree configuration (and optionally to Pinctrl overview) must be added in the #DT configuration (board level) and/or #DT configuration examples.

3.3. DT configuration examples[edit source]

This OPTIONAL chapter must provide an example of how to configure the DT to adapt it to a new board.

4. How to configure the DT using STM32CubeMX[edit source]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
STM32CubeMX may not support all the properties described in DT binding files listed in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties, and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

5. References[edit source]

Refer to the following links for additional information: