- Last edited 8 months ago ago
Arm CoreSight overview
1 Article purpose
The purpose of this article is to give information about the Arm® CoreSight™ hardware subsystem.
It explains what are the principle peripherals of this subsystem.
2 Peripheral overview
Arm®CoreSight™ products include a wide range of trace macrocells for Arm® processors, system and software instrumentation and a comprehensive set of IP blocks to enable the debug & trace of the most complex, multi-core SoCs.
Arm® has defined an open CoreSight architecture to allow SoC designers to add debug & trace capabilities for other IP cores in to the CoreSight infrastructure.
2.1 Components description
The debug features are based on Arm® CoreSight™ components
|Arm® CoreSight™ components||STM32MP13x lines||STM32MP15x lines|
|SWJ-DP: JTAG/Serial-wire debug port|
|AXI-AP: AXI access port|
|AHB-AP: AHB access port|
|APB-AP: APB access port|
|ITM: Instrumentation Trace Macrocell|
|DWT: Data Watchpoint and Trace|
|ETM: Embedded Trace Macrocell|
|ETF: Embedded Trace FIFO|
|TPIU: Trace Port Interface Unit|
|SWO: Serial Wire Output|
|CTI: Cross Trigger Interface|
|CTM: Cross Trigger Matrix|
|TSGEN: Timestamp Generator|
|STM: System Trace Macrocell|
More information about these components can be found in the Arm® website 
The supported debug features are described in the Debug support (DBG) chapter of the reference manual. Refer to: