Arm CoreSight overview

Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to give information about the Arm® CoreSight hardware subsystem.
It explains what are the principle peripherals of this subsystem.

2 Peripheral overview[edit]

Arm®CoreSight products include a wide range of trace macrocells for Arm® processors, system and software instrumentation and a comprehensive set of IP blocks to enable the debug & trace of the most complex, multi-core SoCs. Arm® has defined an open CoreSight architecture to allow SoC designers to add debug & trace capabilities for other IP cores in to the CoreSight infrastructure.

Alternate text
STM32MP15 CoreSight overview

2.1 Components description[edit]

The debug features are based on Arm® CoreSight™ components

Arm® CoreSight™ components STM32MP13x lines Warning.png STM32MP15x lines More info.png
SWJ-DP: JTAG/Serial-wire debug port Yes Yes
AXI-AP: AXI access port Yes Yes
AHB-AP: AHB access port No Yes
APB-AP: APB access port Yes Yes
ITM: Instrumentation Trace Macrocell Yes Yes
DWT: Data Watchpoint and Trace Yes Yes
ETM: Embedded Trace Macrocell Yes Yes
ETF: Embedded Trace FIFO Yes Yes
TPIU: Trace Port Interface Unit Yes Yes
SWO: Serial Wire Output No Yes
CTI: Cross Trigger Interface Yes Yes
CTM: Cross Trigger Matrix Yes Yes
TSGEN: Timestamp Generator Yes Yes
STM: System Trace Macrocell No Yes

More information about these components can be found in the Arm® website [1]

2.2 Features[edit]

The supported debug features are described in the Debug support (DBG) chapter of the reference manual. Refer to:


3 References[edit]