ETM internal peripheral

1. Article purpose

The purpose of this article is to:

• briefly introduce the ETM peripheral and its main features
• indicate the level of security supported by this hardware block
• explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
• explain, when necessary, how to configure the ETM peripheral.

2. Peripheral overview

The ETM peripheral is used to log the Cortex-A7 execution trace into the embedded trace FIFO (ETF). Once in the ETF buffer, the trace can directly be dumped from the Cortex^®-A7 or to the trace port interface unit (TPIU), connected to an external probe able to decode it.
This peripheral has two instances, one for each Cortex^®-A7 core.

2.1. Features

Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are really implemented.

2.2. Security support

The ETM is a non secure peripheral.

3. Peripheral usage and associated software

3.1. Boot time

The ETM can be used to debug the boot sequence using external probe.

3.2. Runtime

3.2.1. Overview

The ETM can be used to debug the run time application using external probe.

3.2.2. Software frameworks

There is no software dedicated to the ETM internal peripheral delivered with STM32MPU ecosystem. Nevertheless, the ETM trace can be captured using an external probe.

3.2.3. Peripheral configuration

Configuration of the ETM is done via JTAG scripts. Those scripts must be built by user thanks to STM32MP15 reference manuals .

3.2.4. Peripheral assignment

Internal peripherals assignment table template

| rowspan="2" | Trace & Debug
| rowspan="2" | ETM
| ETM0
| ✓
| ✓
|
|
|-
| ETM1
| ✓
| ✓
| 
|
|-

|}

Embedded trace macrocell

Cortex^®

debug and test protocol, named from the Joint Test Action Group that developed it