Arm CoreSight overview

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1. Article purpose

The purpose of this article is to give information about the Arm^® CoreSight^™ subsystem.
It explains what are the principle peripherals of this subsystem.

2. Peripheral overview

Arm^® CoreSight^™ products include a wide range of trace macrocells for Arm^® processors, system and software instrumentation and a comprehensive set of IP blocks to enable the debug & trace of the most complex, multi-core SoCs. Arm^® has defined an open CoreSight architecture to allow SoC designers to add debug & trace capabilities for other IP cores in to the CoreSight infrastructure.

CoreSight overview

2.1. Components description

The debug features are based on Arm® CoreSight™ components:
• SWJ-DP: JTAG/Serial-wire debug port
• AXI-AP: AXI access port
• AHB-AP: AHB access port
• APB-AP: APB access port
• ITM: Instrumentation Trace Macrocell
• DWT: Data Watchpoint and Trace
• ETM: Embedded Trace Macrocell
• ETF: Embedded Trace FIFO
• TPIU: Trace Port Interface Unit
• SWO: Serial Wire Output
• CTI: Cross Trigger Interface
• CTM: Cross Trigger Matrix
• TSGEN: Timestamp Generator
• STM: System Trace Macrocell
More information about these components can be found in the Arm® documents referenced

2.2. Features

Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are really implemented.

2.3. Security support

The Arm^® CoreSight^™ is a non secure peripheral.

3. Peripheral usage and associated software

3.1. Boot time

The Arm^® CoreSight^™ is not used at boot time.

3.2. Runtime

3.2.1. Overview

Internal peripheral generates a trace stream, namely instruction traces, depending on instructions and events happening when CPUs are executing a program. This encoded stream can be then stored in a dedicated SRAM via a buffer and/or extracted through an external port.

3.2.2. Software frameworks

Internal peripherals software table template

| Trace & Debug
|  Arm CoreSight 
| 
| 
| 
|
|-
|}

3.2.3. Peripheral configuration

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

debug and test protocol, named from the Joint Test Action Group that developed it

Advanced high-performance bus

Advanced peripheral bus

Instruction trace Macrocell

Embedded trace macrocell

System trace module

Cortex^®