Arm CoreSight overview

This article gives information about the ARM^® Coresight subsystem.
It explains what are the principle peripherals of this subsystem, how they interact, and how to activate them.

1. Framework purpose

ARM^® Coresight products include a wide range of trace macrocells for ARM^® processors, system and software instrumentation and a comprehensive set of IP blocks to enable the debug & trace of the most complex, multi-core SoCs. ARM^® has defined an open CoreSight architecture to allow SoC designers to add debug & trace capabilities for other IP cores in to the CoreSight infrastructure.
Coresight can be used in many different use cases, as mentioned in How to use Coresight section.

2. System overview

Coresight Overview

2.1. Components description

The debug features are based on Arm® CoreSight™ components:
• SWJ-DP: JTAG/Serial-wire debug port
• AXI-AP: AXI access port
• AHB-AP: AHB access port
• APB-AP: APB access port
• ITM: Instrumentation Trace Macrocell
• DWT: Data Watchpoint and Trace
• ETM: Embedded Trace Macrocell
• ETF: Embedded Trace FIFO
• TPIU: Trace Port Interface Unit
• SWO: Serial Wire Output
• CTI: Cross Trigger Interface
• CTM: Cross Trigger Matrix
• Timestamp Generator
• STM: System Trace Macrocell
More information about these components can be found in the Arm® documents referenced

2.2. Features

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

3. Principle

Internal peripheral generates a trace stream, namely instruction traces, depending on instructions and events happening when CPUs are executing a program. This encoded stream can be then stored in a dedicated SRAM via a buffer or extracted through an external JTAG port.

4. Configuration

4.1. Kernel configuration

Detailed procedure on how to activate the Coresight subsystem :

• Coresight kernel configuration

4.2. Device tree configuration

Detailed DT configuration for STM32 internal peripherals:

• Coresight device tree configuration

5. How to use the subsystem

See examples in How to use Coresight.

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

debug and test protocol, named from the Joint Test Action Group that developed it

Advanced high-performance bus

Advanced peripheral bus

Instruction trace Macrocell

Embedded trace macrocell

System trace module

Device tree

Cortex^®