1. Purpose[edit source]
This article explains how to change the CPU operating point (also known as OPP): an operating point corresponds the frequency of the processor and the voltage that needs to be supplied to sustain it.
2. Hardware side[edit source]
On STM32MP1 series, the Cortex-A7 core is:
- clocked by the PLL1 from the RCC internal peripheral: the PLL1P output frequency can be directly propagated to the core or it can go through an intermediate MPUDIV dividor,
- supplied with VDDcore voltage.
In the part number, the increased frequency field tells that the device can be clocked up to 800 MHz when it is set. Otherwise, the frequency must be kept below 650 MHz.
3. Software side[edit source]
3.1. For ecosystem release v1.2.0[edit source]
The ecosystem release v1.2.0 is backward compatible with the previous deliveries, so it is still possible to set the CPU frequency in TF-A device tree, as described in the paragraph below. If your part number supports increased frequency, ensures that VDDcore minimum voltage is increased from 1.2V to 1.35V while running above 650 MHz: this is done in the regulators node of the board device tree.
But, by default, the ecosystem release v1.2.0 does not set any configuration for the PLL1 in the FSBL (TF-A) and instead, TF-A automatically selects the operating point that is suitable for the current part number according to the OPP table below (embedding frequency and voltage couples), defined in the SOC device tree fdts/stm32mp157c.dtsi .
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-microvolt = <1200000>;
opp-supported-hw = <0x1>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1350000>;
opp-supported-hw = <0x2>;
};
};
Notes:
- The operating point supported by the increased frequency part numbers is identified by the opp-supported-hw property set to 0x2,
- This same OPP table must also be present in the Linux SOC device tree fdts/stm32mp157c.dtsi ,
- It is possible to do a mix, specifying the PLL1 configuration (without OPP table) in TF-A device tree whereas Linux will use the OPP table to increase the CPU frequency once started.
3.2. For ecosystem release ≤ v1.1.0[edit source]
The Cortex-A7 core frequency is selected at boot time, by the FSBL (TF-A), following the Clock device tree configuration - Bootloader specific syntax. The frequency is set to 650 MHz by default, as shown in STM32MP15 clock tree. This configuration is set in TF-A device tree, for instance fdts/stm32mp157a-dk1.dts file for STM32MP157C-DK1 board.
&rcc {
...
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
};
...
};
The user can reduce this frequency by changing the above configuration, whether manually or via STM32CubeMX graphical user interface that allows to generate the corresponding device tree file.