1. Purpose[edit source]
This article explains how to change the processor operating point: an operating point corresponds the frequency of the processor and the corresponding voltage that needs to be supplied to sustain it.
2. Hardware side[edit source]
On STM32MP1 series, the Cortex-A7 core is clocked by the PLL1 from the RCC internal peripheral: the PLL1P output can be directly propagated to the core or it can go through an intermediate MPUDIV dividor.
3. Software side[edit source]
3.1. For ecosystem release v1.2.0[edit source]
The ecosystem release v1.2.0 is backward compatible with the previous deliveries, so it is still possible to set the Cortex-A7 core frequency by changing the PLL1 configuration in TF-A device tree, for instance fdts/stm32mp157a-dk1.dts file for STM32MP157C-DK1 board. This change can also be done in STM32CubeMX graphical user interface that allows to generate the corresponding device tree file.
But, by default, the ecosystem release v1.2.0 does not set any configuration for the PLL1 in the FSBL (TF-A) and instead, TF-A automatically sets the processor frequency to 650 MHz or 800 MHz at boot time, in line with the current part number it is running on.
3.2. For ecosystem release ≤ v1.1.0[edit source]
The Cortex-A7 core frequency is selected at boot time, by the FSBL, following the Clock device tree configuration - Bootloader specific. The frequency is set to 650 MHz by default, as shown in STM32MP15 clock tree.
The user can reduce this frequency by changing the PLL1 configuration in TF-A device tree, for instance fdts/stm32mp157a-dk1.dts file for STM32MP157C-DK1 board. This change can also be done in STM32CubeMX graphical user interface that allows to generate the corresponding device tree file.