1. S2-LP bring-up good practices
2. Introduction
This article presents the complete set of bring-up guidelines and RF configuration practices for the S2‑LP sub‑GHz transceiver. It consolidates hardware constraints, digital and analog register configurations, clocking requirements, RF calibration procedures, and protocol‑level recommendations. Every section restates and expands the technical details from the source document while remaining strictly aligned with the official content.
3. SDN management
3.1. SDN pin requirements
- The SDN pin must be driven by an MCU GPIO. This is mandatory to ensure correct device reset and power management.
- The SDN pin must not be tied to GND. Doing so prevents the S2‑LP from performing required initialization sequences.
3.2. SDN timing at power-up
- As stated in Table 36 of S2-LP datasheet, when the S2-LP VDD rises, the SDN signal must respect a minimum hold time of 1 µs before toggling. This ensures proper internal stabilization.
- The S2-LP datasheet (Figure 7) specifies graphically the start-up phase.
3.3. Register programming after reset
- After issuing a reset, register access must start only when the S2-LP reaches READY state.
- The READY state may be detected by:
- Polling MC_STATE0 or ..
- ... Monitoring GPIO0 in inverted POR mode (default). This is the recommended method.
- Even though a 2 ms recommended reset delay exists, READY polling remains mandatory.
4. Power-up and reset conditions
- In systems where both MCU and S2‑LP power domains rise together, careful SDN/VDD sequencing prevents incorrect initialization.
- Improper sequencing may lead to stalled startup or unresponsive SPI.
5. Analog and digital domains
5.1. Digital divider settings
The digital clock (c_dig) may differ from the analog clock depending on crystal frequency.
See S2-LP datasheet part 4.7 for more information:
- For 24/25/26 MHz crystals, PD_CLKDIV must be set to 1.
- For 48/50/52 MHz crystals, PD_CLKDIV stays at default (0).
- Divider configuration must be applied in Stand-by mode to avoid timing corruption.
5.1.1. Digital C configuration - code recommendations
- Code recommendations (S2-LP DK) – change register in Stand-by mode
if(((s_lXtalFrequency<DIG_DOMAIN_XTAL_THRESH) && (xState==S_ENABLE)) || ((s_lXtalFrequency>DIG_DOMAIN_XTAL_THRESH) && (xState==S_DISABLE)))
{
S2LPSpiCommandStrobes(CMD_STANDBY);
do{
for(volatile uint8_t i=0; i!=0xFF; i++);
S2LPRefreshStatus(); // add a timer expiration callback
}while(g_xStatus.MC_STATE!=MC_STATE_STANDBY);
xState = (SFunctionalState)!xState;
S2LPRadioSetDigDiv(xState);
S2LPSpiCommandStrobes(CMD_READY);
}
6. Crystal, clock, and oscillator settings
6.1. High-speed crystal frequency options
Supported HS crystal frequencies: 24, 25, 26, 48, 50, 52 MHz.
6.2. GM_CONF (XO driver transconductance)
- These settings tune the initial drive strength of the XO amplifier.
- Correct values ensure stable crystal startup, especially in cold‑start conditions.
6.3. Clock filtering (CNTCONF & CKFILT_CONF)
- Digital clock filtering prevents jitter propagation into digital logic.
6.4. Load capacitance selection
It's important to review and start from crystal manufacturer’s load capacitance.
- It's possible to include 2 pF PCB parasitics.
- Compute soldered capacitance: C_load ≈ 2 × (C_xtal − C_PCB).
Example:
- C_xtal = 8 pF (NDK Xtal mounted on ST kits)
- C_load ≈ 12 pF.
- Load capacitors may require fine tuning on the final board.
7. VCO charge pump settings
7.1. VCO charge pump configuration
- PLL_CP_ISEL and PLL_PFD_SPLIT_EN depend on RF band and crystal frequency.
- Find examples in the table below
7.2. VCO calibration
- Automatic calibration mode (default) is recommended.
7.3. Band Selector (SYNT3 Register)
It's important and recommended to specify band selector in SYNT3 register:
- High band (826–1055 MHz): B = 4.
- Mid band (413–527 MHz): B = 8.
8. Intermediate frequency settings
See recommended register settings for intermediate frequency, which depends on Xtal values
| HS Xtal | IF_OFFSET_ANA | IF_OFFSET_DIG |
| 24MHz | 0xCF | 0xCF |
| 25MHz | 0xC2 | 0xC2 |
| 26MHz | 0xB7 | 0xB7 |
| 48MHz | 0x35 | 0xCF |
| 50MHz | 0x2F | 0xC2 |
| 52MHz | 0x29 | 0xB7 |
9. TCXO use case
- TCXO behaves similarly to a crystal except you need to configure it:
- Set the bit to 1: EXT_REF=1 in XO_RCO_CONFIG0
- TCXO enable pin must be controlled by MCU.
A guard delay must be added before Tx/Rx to allow TCXO stabilization, without stabilization, the S2‑LP PLL may fail to lock.
10. SMPS and external LDO configuration
10.1. External LDO Case (no internal SMPS)
In case S2-LP SMPS is not used:
- An external LDO must supply SMPS2 pin.
- EXT_SMPS must be set to 1. (register PM_CONF4)
- MCU must control LDO enable and guard time should be used to ensure stable LDO output.
10.2. Recommended SMPS frequency configuration
11. CSMA good practices
CSMA recommendations
- Disable CS_Blanking (ANT_SELECT_CONF register) to avoid wrong behavior
- To avoid 0x64 state issue (when initiating Tx command)
- Use only CS_mode = 0 (RSSI_FLT register)
- Activate Sleep mode B when using CSMA – to retain Tx FIFO when in sleep mode
- SLEEP_MODE_SEL = 1 of PM_CONF0 register
- When MAX_BO_REACHED IRQ is raised, two possible cases:
- Either the channel is not clear on last CSMA Rx and Tx is cancelled
- Or the channel is clear on last CSMA Rx (even if MAX_BO_REACHED is raised) and Tx is done
⇒If Tx is done, TX_Done IRQ is raised at the end of transmission
⇒It is possible to read RSSI_LEVEL register when MAX_BO_REACHED IRQ is raised to anticipate S2-LP decision
12. Clock recovery settings (CLOKREC registers)
Default values are not recommended.
Standard configuration
- CLOCKREC2 = 0x28 / CLOCKREC1 = 0x58
Short preamble configuration
- CLOCKREC2 = 0x28 / CLOCKREC1 = 0x28
4-(G)FSK demodulator
- CLOCKREC2 = 0xC0 / CLOCKREC1 = 0x48 (RSSI threshold adjustment needed)
OOK/ASK demodulator
- CLOCKREC2 = 0x28 / CLOCKREC1 = 0x28
- Optionally AFC2 setting may be needed to improve Rx (long series of ‘1’s) : AFC2 = 0xC0
Data rate dispersion on transmitter side (higher than +/-3%)
- CLOCKREC2 = 0x36 / CLOCKREC1 = 0x26
- RSSI_TH adjustment : to be set 2~3 dBs below Rx sensitivity level
13. AFC settings and configuration
Three kinds of tolerances to take into account
- Initial frequency offset: measured at ambient temperature (+ 25°C)
- Temperature frequency offset: drift according to “S” curve
- Aging frequency offset
All tolerance given in +/-ppm
TCXO has lower drift than standard Xtal but the price is higher
Order of ideas (using Xtal of S2-LP kits):
| TCXO | Standard Xtal | Calibration | |
| Initial frequency offset | +/-1,5ppm | +/-10ppm | Can be calibrated at production |
| Temperature frequency offset
(industrial range) |
+/-1ppm | +/-12ppm | No
Can be mitigated in case reduced temperature range (indoor application) |
| Aging frequency offset | +/-1ppm/year
+/-5ppm max |
+/-1ppm/year | No |
13.1. AFC theory explanation for Tx and Rx applications
14. AFC register recommendations
Basic settings: recommended if no specific frequency offset target
AFC2 = 0xC8 (AFC mode 0 activated)
AFC1 = 0x18 (default)
AFC0 = 0x23: improve interferer immunity
Performance settings: larger frequency offset recovery with lower Rx bandwidth
To be used only in Rx LCD mode conditions (no continuous Rx)
AFC2 = 0xE8 (AFC mode 1 activated)
AFC1 = 0x10
AFC0 = 0x23: improve interferer immunity
RSSI threshold adjustment is important and recommended:
- RSSI_TH should be tuned 2~3dB below Rx sensitivity level
Rx timeout method preferred: Rx processing shouldn’t be continuous – reset AFC every time Rx re-started
14.1. AFC correction (AFC_CORR register)
14.1.1. Examples of Radio channel configuration depending of crystal ppm
Realistic Radio channel configuration vs Xtal tolerances – 2-(G)FSK use cases
Assuming:
- Cumulated frequency offset (Tx and Rx devices) not more than 2 x frequency deviation
- Receiver Bandwidth = 2 x frequency deviation + data rate + Frequency offset
| Xtal type | Application | Xtal ppm | Radio Band | Frequency deviation | Data Rate | Receiver Bandwidth |
| TCXO | TCXO calibration | +/-6ppm | 868MHz | 5kHz | 5kbps | 20kHz |
| TCXO | TCXO calibration | +/-6ppm | 433MHz | 2,5kHz | 5kbps | 15kHz |
| Standard Xtal | Xtal calibration
In-door use |
+/-16ppm | 868MHz | 30kHz | 1kbps | 75kHz |
| Standard Xtal | Xtal calibration
In-door use |
+/-16ppm | 433MHz | 15kHz | 1kbps | 40kHz |
| Standard Xtal | Xtal calibration
Out-door use |
+/-22ppm | 868MHz | 40kHz | 20kbps | 120kHz |
| Standard Xtal | Xtal calibration
Out-door use |
+/-22ppm | 433MHz | 20kHz | 20kbps | 70kHz |
| Standard Xtal | no calibration
Out-door use |
+/-32ppm | 868MHz | 60kHz | 40kbps | 190kHz |
| Standard Xtal | Xtal calibration
Out-door use |
+/-32ppm | 433MHz | 30kHz | 40kbps | 115kHz |
15. AGC recommendations
- Frequency modulations (FSK, (G)FSK, ..):
- Default settings can be used AGCCTRL0 to AGCCTRL5 registers
- OOK modulation
- Default settings can be used up to -20dBm
- Tunings required for better management of high Rx levels:
| Register name | AGCCTRL5 | AGCCTRL4 | AGGCTRL3 | AGCCTRL2 | AGCCTRL1 | AGGCTRL0 |
| Register address | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E |
| Register value | 0x80
(default) |
0x00 | 0x10
(default) |
0x42 | 0x59
(default) |
0x82 |
16. Frequency offset compensation after calibration
It is recommended to compensate the frequency offset by software, as there is no frequency offset register: you will always have better accuracy of calibration when compensating SYNTx registers by software.
Granularity directly depends on:
- Xtal frequency
- B factor: four for high band (from 826 to 1055MHz) or eight for middle band (from 413 to 527MHz)
- D is the reference divider (REFDIV of XO_RCO_CONFIG0 register)
Frequency base synthetizer granularity (REFDIV = 0 / D=1):
| 413 to 527MHz | 826 to 1055MHz | |
| 24 MHz Xtal | 5,7 Hz | 11,4 Hz |
| 25 MHz Xtal | 6 Hz | 12 Hz |
| 26 MHz Xtal | 6,2 Hz | 12,4 Hz |
| 48 MHz Xtal | 11,4 Hz | 22,9 Hz |
| 50 MHz Xtal | 11,9 Hz | 23,8 Hz |
| 52 MHz Xtal | 12,4 Hz | 24,8 Hz |
17. SPI communication requirements
18. Hardware recommendations
18.1. Crystal centering validation
The Xtal should be properly loaded, with the correct load capacitances, to ensure oscillation occurs at the desired Xtal frequency (+/− ppm, according to the Xtal specification.
If the Xtal is not properly centered, the S2-LP PLL may not lock (0x14 state) = LOCK STATE
18.1.1. Continuous wave hardware test
- Perform the CW test with a spectrum analyzer to check if main frequency does match the desired frequency.
- Set MOD_TYPE = 7 (MOD2) / TX_SOURCE = PN9 (PCKTCTRL1).
- Send the TX command (command code: 0x60).
- Verify that the RF peak is generated at the desired frequency.
18.2. Output digital clock on S2-LP GPIO (FDIG/256)
- GPIO output can expose internal digital clock.
/* Disable the c divider to measure the max frequency of the c. */
//S2LPRadioSetDigDiv(S_DISABLE);
tmp=0x55;
SdkEvalSpiWriteRegisters(0x6C, 1, &tmp);
/* GPIO2 to the c output */
tmp=0x88|0x02;
SdkEvalSpiWriteRegisters(0x02, 1, &tmp);
SdkEvalSpiReadRegisters(0xF1, 1, &tmp);
if((tmp&0x80)==0)
{/* CUT 1.x */
tmp=0x9E;
}
else
{
tmp=0x90;
}
SdkEvalSpiWriteRegisters(0x04, 1, &tmp);
18.3. VREF_VCO capacitor
A common error is not setting the correct capacitance value on the VREFVCO pin.
A 470 pF capacitor is mandatory, as in the reference schematic BOM.
Otherwise, the PLL may fail to lock (0x14 state).
18.4. SMPS inductor requirements
Cautious on the SMPS inductor. The correct choice for L0 on the BOM is a typical 10 µH inductor with a ±10% tolerance. It should have a rated current of at least 100 mA.
Its DC resistance should be as low as possible to maximize SMPS efficiency; around 1 Ω is typically a good value, but lower is better.
- 10 µH ±10%, ≥ 100 mA, low DCR.
19. Test TX modes for certification
S2-LP proposes a Tx test mode to simplify the certification process.
Two continuous Tx test modes are available: CW and PN9.
For Tx CW configuration:
- Set MOD_TYPE = 7, which corresponds to unmodulated mode, in the MOD2 register.
- Set TX_SOURCE = 3, which corresponds to PN9, in the PCKTCTRL1 register.
- Send the Tx command.
- Use the SABORT command to stop the test.
For Tx PN9 configuration:
- Keep the application modulation enabled by using the MOD_TYPE setting in the MOD2 register.
- Set TX_SOURCE = 3, which corresponds to PN9, in the PCKTCTRL1 register.
- Send the Tx command.
- Use the SABORT command to stop the test.
20. Packet handler usage (Rx and Tx)
It is recommended to activate the FIFO underflow and overflow error interrupts.
Sanity check:
- Enable FIFO underflow and overflow interrupts for both the Tx and Rx FIFOs.
- In the interrupt handler:
- Send the SABORT command to stop Tx or Rx.
- Flush the Tx and Rx FIFOs.
20.1. S2-LP commands
S2-LP command list to take into account
Tx Command: to start transmission (either packet mode or test mode) It is not recommend to read back S2-LP state as transient states happen before going into Tx state
Rx command: to start reception (either packet mode or test mode) It is not recommend to read back S2-LP state as transient states happen before going into Tx state
Stand-by / Sleep commands: to enter S2-LP low-power modes with register retention
Ready command: to exit low-power modes (Stand-by or Sleep) – safer to wait for Ready command confirmation before issuing another SPI transaction
Tx or Rx Flush FIFO commands: sanity check to make sure S2-LP FIFOs are empty
Sabort command: to be used when FIFO errors occur or to stop Reception (if no timeout is used)
- To be used also to stop Tx and Rx test modes
- If Tx packet mode is used no need for Sabort command
SRES command: can be used to perform SW reset of S2-LP chip (default register value)
21. RSSI threshold usage
The same RSSI threshold register, RSSI_THR, is used for different purposes.
- In Rx sniff mode, it defines the RSSI level at which RSSI detection is asserted.
- If the RSSI threshold is detected, S2-LP continues reception
- until the end of packet reception if the SYNC pattern, or PQI, is matched, or
- until the Rx timeout expires.
- In CSMA, it defines the RSSI level at which transmission is considered busy or delayed.
- In AFC, it defines the RSSI level at which the AFC algorithm starts tracking frequency offset compensation.
It is recommended to avoid setting the threshold too low, to prevent false AFC compensation due to RF noise.
- In CS_Blanking, it defines the RSSI threshold at which the S2-LP digital part starts acquiring digital samples from the analog front end.
This is used to:
Limit or avoid false sync detections when the SYNC pattern is short, less than 20 bits
Trigger direct Rx FIFO filling upon a radio event when the RSSI threshold is reached
Good to know:
If CS_Blanking is not activated, it is possible to receive packets with an RSSI level lower than the RSSI_THR value, as indicated by the RSSI_LEVEL register.
The RSSI threshold is compared at the chip pin level, not at the antenna connector level. As a result, it is possible to measure a signal strength that is about 2 dB lower than the value at the antenna connector.
22. S2-LP States
- MC_STATE0 enumerates all radio states.
- States include Ready, Sleep, LockST, Rx, Tx, Wait_Sleep.