Introduction to External Memory Manager custom driver configuration

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1. Introduction to External Memory Manager custom Driver

The External Memory Manager (EMM) module was implemented to assist in the development of ROMless applications, although it can be used in other applications that use external memory in raw mode (without any file system management). It is an STM32 middleware component, providing two levels of services:

  • A unique API to access all supported types of memory.
  • A BOOT system API to launch an application originally stored on external memory.

EMM services can also be used to build External Memory Loaders.

2. External Memory Manager middleware overview

The External Memory Manager middleware provides a unique interface for all supported memories. It contains several drivers that can be used to address physical memories depending on memory types, and hardware configurations.

It is ST's solution to support various external memories, such as serial NOR flash, PSRAM, and SD cards, on STM32 MCUs. It consists of several different drivers:

  • NOR_FLASH driver: this driver is dedicated to Nor Flash memories, and allows the user to initialize and configure memory access, based on information stored in SFDP tables of the memory
  • PSRAM driver: this driver is dedicated to PSRAM memories. Memory access is performed in Memory Map mode only.
  • SDCARD driver: this driver is dedicated to SD Card memories.
  • CUSTOM Driver: this driver is designed to allow memory configuration and content access, based on a configuration file (information used for memory configuration and access is stored in the configuration file, and does not rely on what is present in memory SFDP tables for instance). This driver could be used to drive Nor flash, PSRAM, HyperRAM and EEPROM memories.
  • USER Driver: this driver is left for user implementation. Only APIs are provided, with empty function bodies (user implementation required)

2.1. External Memory Manager middleware architecture

In the figure above, the EMM middleware architecture is described with the interconnections between drivers, firmware, middleware, and application.

For each memory type, the user has to select the type of EMM driver to be used:

Driver type Could be used to manage NOR memories Could be used to manage RAM memories Could be used to manage SD CARD memories
PSRAM driver Yes
NOR SFDP driver Yes (If SFDP compatible memory)
SD CARD driver Yes
CUSTOM Yes Yes
USER Yes (User implementation) Yes (User implementation) Yes (User implementation)

2.2. External Memory Manager APIs

The below table provides a summary of available External Memory Manager APIs per driver:

API NOR FLASH driver PSRAM Driver SDCARD driver CUSTOM driver USER Driver
EXTMEM_Init Yes Yes Yes Yes Yes (User Implementation)
EXTMEM_DeInit Yes Yes Yes Yes Yes (User Implementation)
EXTMEM_Read Yes - Yes Yes Yes (User Implementation)
EXTMEM_Write Yes - Yes Yes Yes (User Implementation)
EXTMEM_WriteInMappedMode Yes - - Yes Yes (User Implementation)
EXTMEM_EraseSector Yes - Yes Yes Yes (User Implementation)
EXTMEM_EraseAll Yes - Yes Yes Yes (User Implementation)
EXTMEM_GetInfo Yes - Yes Yes Yes (User Implementation)
EXTMEM_MemoryMappedMode Yes Yes - Yes Yes (User Implementation)
EXTMEM_GetMapAddress Yes Yes - Yes Yes (User Implementation)

When using the Custom driver, the application calls the standard EXTMEM_* APIs shown above. EMM then dispatches internally to the Custom driver functions described in the next section.

2.3. Custom driver implementation functions

The External Memory Manager Custom driver implements the standard EXTMEM_* APIs through EXTMEM_DRIVER_CUSTOM_* functions. These functions are invoked by EMM when the Custom driver is selected (they are not intended to be the primary external API).

EXTMEM API (user) Custom driver function Description Parameters Availability
EXTMEM_Init EXTMEM_DRIVER_CUSTOM_Init This function manages memory initialization EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user
uint32_t ClockInput: clock frequency applied on the HW link used by the memory 		All memory types
EXTMEM_DeInit EXTMEM_DRIVER_CUSTOM_DeInit This function manages memory deinitialization EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user All memory types
EXTMEM_Read EXTMEM_DRIVER_CUSTOM_Read This function manages memory reading EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user
uint32_t Address: memory address to read from

uint8_t* Data: destination data buffer

uint32_t Size: size in bytes 		NORFlash
EXTMEM_Write EXTMEM_DRIVER_CUSTOM_Write This function manages memory writing EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user
uint32_t Address: memory address to write at

const uint8_t* Data: source data buffer

uint32_t Size: size in bytes 		NORFlash
EXTMEM_WriteInMappedMode EXTMEM_DRIVER_CUSTOM_WriteInMappedMode This function manages memory writing in memory mapped mode EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user
uint32_t Address: memory address to write at

const uint8_t* Data: source data buffer

uint32_t Size: size in bytes 		NORFlash
EXTMEM_EraseSector EXTMEM_DRIVER_CUSTOM_EraseSector This function manages memory sector erase EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user
uint32_t Address: memory address in sector to erase

uint32_t Size: size in bytes 		NORFlash
EXTMEM_EraseAll EXTMEM_DRIVER_CUSTOM_MassErase This function manages complete memory erase EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user NORFlash
EXTMEM_GetInfo EXTMEM_DRIVER_CUSTOM_GetInfo This function allows to retrieve memory information EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user
EXTMEM_DRIVER_CUSTOM_MemInfoTypeDef *MemInfo: memory information 		NORFlash
PSRAM
HyperRAM
EXTMEM_MemoryMappedMode EXTMEM_DRIVER_CUSTOM_Enable_MemoryMappedMode This function allows to enable the memory mapped mode EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user NORFlash
PSRAM
HyperRAM
EXTMEM_MemoryMappedMode EXTMEM_DRIVER_CUSTOM_Disable_MemoryMappedMode This function allows to disable the memory mapped mode EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user NORFlash
PSRAM
HyperRAM
EXTMEM_GetMapAddress EXTMEM_DRIVER_CUSTOM_GetMapAddress This function returns the mapped address of the memory EXTMEM_DRIVER_CUSTOM_ObjectTypeDef *CustomObject: Memory configuration object defined by the user
uint32_t *BaseAddress: returned value containing the memory base mapped address 		NORFlash
PSRAM
HyperRAM

2.4. Custom driver user callback implementation

When a configuration step requires application-specific processing, the custom driver can call a user-defined callback function, EXTMEM_DRIVER_CUSTOM_UserCallback(). This callback is configured in the memory object by setting RegisterConfig[n].ConfigStepType to a user-callback type and by filling in the corresponding CBConfigStep fields. The APIs mentioned above depend on the memory configuration of the object, whose structure is described in the next section.

3. Custom memory configuration

To add a memory, the structure EXTMEM_DRIVER_CUSTOM_ObjectTypeDef must be filled with the relevant information corresponding to the chosen memory. The structure can be sectioned off as follows:

EXTMEM_DRIVER_CUSTOM_ObjectTypeDef

General parameters 

.MemType                    /* Mandatory */
.MemStandard                /* Mandatory */
.MemSize                    /* Mandatory */
.ResetMethod                /* Mandatory (set UNDEFINED if not used) */
.SampleShiftCfg             /* Mandatory (set to NONE if not used) */
.ResetDelay                 /* Mandatory (set to 0 if no delay is required) */
.MemChipSelectHighTimeCycle /* Mandatory */

StartupConfig parameters 

.StartupConfig.Frequency          /* Mandatory */
.StartupConfig.CommandRead        /* Mandatory for NORFlash/PSRAM, not used for HyperRAM */
.StartupConfig.CommandWrite       /* Mandatory for NORFlash/PSRAM, not used for HyperRAM */
.StartupConfig.DummyCycleRead     /* Mandatory for NORFlash/PSRAM, not used for HyperRAM */
.StartupConfig.DummyCycleWrite    /* Mandatory for NORFlash/PSRAM, not used for HyperRAM */
.StartupConfig.DummyRegisterRead  /* Mandatory for NORFlash/PSRAM, not used for HyperRAM */
.StartupConfig.AccessMode         /* Mandatory */
.StartupConfig.OptWriteAccessMode /* Optional (only if write access mode differs from AccessMode) */
.StartupConfig.InstructionSize    /* Mandatory for NORFlash/PSRAM, not used for HyperRAM */
.StartupConfig.AddressSize        /* Mandatory */
.StartupConfig.DqsMode            /* Mandatory (disable if not used) */

Register configuration parameters 

.NbRegisterConfig                  /* Optional (0 if no register/config steps are required) */
.RegisterConfig[n].ConfigStepType  /* Optional (only if NbRegisterConfig > 0) */

RegisterConfig[n].RWConfigStep parameters 

.RegisterConfig[n].RWConfigStep.RegisterAddress       /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].RWConfigStep.CommandRegisterWrite  /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].RWConfigStep.CommandRegisterRead   /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].RWConfigStep.CommandRegisterReadAW /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].RWConfigStep.RegisterValue         /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].RWConfigStep.RegisterExpectedValue /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].RWConfigStep.RegisterMask          /* Optional (depends on ConfigStepType) */

RegisterConfig[n].INSConfigStep parameters 

.RegisterConfig[n].INSConfigStep.CommandRegisterWrite /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].INSConfigStep.CommandRegisterRead  /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].INSConfigStep.Instruction          /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].INSConfigStep.RegisterAddress      /* Optional (depends on ConfigStepType) */
.RegisterConfig[n].INSConfigStep.RegisterValue        /* Optional (depends on ConfigStepType) */

RegisterConfig[n].CBConfigStep parameters 

.RegisterConfig[n].CBConfigStep.Callback /* Optional (only if ConfigStepType is EXTMEM_CUSTOM_CFGSTEP_USER_CALLBACK) */
.RegisterConfig[n].CBConfigStep.UserCtx  /* Optional (only if ConfigStepType is EXTMEM_CUSTOM_CFGSTEP_USER_CALLBACK) */
.RegisterConfig[n].CBConfigStep.Arg0     /* Optional (only if ConfigStepType is EXTMEM_CUSTOM_CFGSTEP_USER_CALLBACK) */
.RegisterConfig[n].CBConfigStep.Arg1     /* Optional (only if ConfigStepType is EXTMEM_CUSTOM_CFGSTEP_USER_CALLBACK) */

OptionalConfig parameters 

.OptionalConfig.Frequency          /* Optional (only if optional configuration is used) */
.OptionalConfig.CommandRead        /* Optional (only if optional configuration is used) */
.OptionalConfig.CommandWrite       /* Optional (only if optional configuration is used) */
.OptionalConfig.DummyCycleRead     /* Optional (only if optional configuration is used) */
.OptionalConfig.DummyCycleWrite    /* Optional (only if optional configuration is used) */
.OptionalConfig.DummyRegisterRead  /* Optional (only if optional configuration is used) */
.OptionalConfig.AccessMode         /* Optional (only if optional configuration is used) */
.OptionalConfig.OptWriteAccessMode /* Optional (only if optional configuration is used) */
.OptionalConfig.InstructionSize    /* Optional (only if optional configuration is used) */
.OptionalConfig.AddressSize        /* Optional (only if optional configuration is used) */
.OptionalConfig.DqsMode            /* Optional (only if optional configuration is used) */

NorFlashConfig parameters (NORFlash memory only) 

.NorFlashConfig.PageSize                /* Mandatory (NORFlash only) */
.NorFlashConfig.SectorSize              /* Mandatory (NORFlash only) */
.NorFlashConfig.MaxSectorEraseTime      /* Mandatory (NORFlash only) */
.NorFlashConfig.MaxChipEraseTime        /* Mandatory (NORFlash only) */
.NorFlashConfig.Startup.SRAccessDetails /* Optional (NORFlash only, set UNDEFINED if no addressed SR access is required) */
.NorFlashConfig.Startup.Cmd_EraseSector /* Mandatory (NORFlash only) */
.NorFlashConfig.Startup.Cmd_MassErase   /* Mandatory (NORFlash only) */
.NorFlashConfig.Startup.Cmd_RDSR        /* Mandatory (NORFlash only) */
.NorFlashConfig.Startup.Cmd_WE          /* Mandatory (NORFlash only) */
.NorFlashConfig.Startup.MatchMask_WEL   /* Mandatory (NORFlash only) */
.NorFlashConfig.Startup.MatchValue_WEL  /* Mandatory (NORFlash only) */
.NorFlashConfig.Startup.MatchMask_WIP   /* Mandatory (NORFlash only) */
.NorFlashConfig.Startup.MatchValue_WIP  /* Mandatory (NORFlash only) */
.NorFlashConfig.OptionalConfigEnable    /* Optional (NORFlash only) */
.NorFlashConfig.Optional.SRAccessDetails /* Optional (only if OptionalConfigEnable is enabled) */
.NorFlashConfig.Optional.Cmd_EraseSector /* Optional (only if OptionalConfigEnable is enabled) */
.NorFlashConfig.Optional.Cmd_MassErase   /* Optional (only if OptionalConfigEnable is enabled) */
.NorFlashConfig.Optional.Cmd_RDSR        /* Optional (only if OptionalConfigEnable is enabled) */
.NorFlashConfig.Optional.Cmd_WE          /* Optional (only if OptionalConfigEnable is enabled) */
.NorFlashConfig.Optional.MatchMask_WEL   /* Optional (only if OptionalConfigEnable is enabled) */
.NorFlashConfig.Optional.MatchValue_WEL  /* Optional (only if OptionalConfigEnable is enabled) */
.NorFlashConfig.Optional.MatchMask_WIP   /* Optional (only if OptionalConfigEnable is enabled) */
.NorFlashConfig.Optional.MatchValue_WIP  /* Optional (only if OptionalConfigEnable is enabled) */

PsramConfig parameters (PSRAM memory only) 

.PsramConfig.WrapSize       /* Mandatory (PSRAM only) */
.PsramConfig.CsBoundarySize /* Mandatory (PSRAM only) */
.PsramConfig.Refresh        /* Optional (PSRAM only, set 0 if not required) */

HyperRamConfig parameters (HyperRAM memory only) 

.HyperRamConfig.HyperbusConfig.RwRecoveryTimeCycle /* Mandatory (HyperRAM only) */
.HyperRamConfig.HyperbusConfig.AccessTimeCycle     /* Mandatory (HyperRAM only) */
.HyperRamConfig.HyperbusConfig.WriteZeroLatency    /* Mandatory (HyperRAM only) */
.HyperRamConfig.HyperbusConfig.LatencyMode         /* Mandatory (HyperRAM only) */
.HyperRamConfig.RamConfig.WrapSize                 /* Mandatory (HyperRAM only) */
.HyperRamConfig.RamConfig.CsBoundarySize           /* Mandatory (HyperRAM only) */
.HyperRamConfig.RamConfig.Refresh                  /* Optional (HyperRAM only, set 0 if not required) */

This object contains the memory configuration and characteristics of the chosen memory. The object structure can vary depending on the configuration chosen by the user, and on the memory type. Multiple examples are available with the custom driver in the "memory" directory, where the structure has already been completed for a wide range of memories.

Each parameter of this structure is listed below with indications on what the parameter is, where the information can be found, and when this parameter is needed.

3.1. General memory configuration

.MemType                             /*!< Common field for memory type        */ \
.MemStandard                         /*!< e.g., Macronix, Micron, etc.        */  \
.MemSize                             /*!< Common field for memory Size        */ \
.ResetMethod                         /*!< Reset method based on 6699h and 9966h instructions */ \
.SampleShiftCfg                      /*!< Sample shift based on memory standard */ \
.ResetDelay                          /*!< Time needed after Reset (in ms, 0 if no required delay) */ \
.MemChipSelectHighTimeCycle          /*!< Common field for memory Chip select high time */ \

3.1.1. MemType

/**
  * @brief Enumeration of supported memory types.
  */
typedef enum
{
  EXTMEM_CUSTOM_HYPERRAM,   /*!< HyperRAM memory type   */
  EXTMEM_CUSTOM_NOR_FLASH,  /*!< NOR Flash memory type  */
  EXTMEM_CUSTOM_PSRAM       /*!< PSRAM memory type      */
} EXTMEM_CUSTOM_MemTypeTypeDef;
  • Description: Specifies the type of external memory device (e.g., HyperRAM, NOR Flash, PSRAM). Determines the protocol, command set, and electrical interface required.
  • Where can I find this information?
    • Memory datasheet: Product overview
    • Memory datasheet: Features section
    • Memory datasheet: Ordering information / part number description
  • When is this parameter needed?
    • Always

3.1.2. MemStandard

 /**
  * @brief Enumeration of supported memory standards.
  */
typedef enum
{
  EXTMEM_CUSTOM_STD_MICRON,       /*!< Micron memory standard         */
  EXTMEM_CUSTOM_STD_MACRONIX,     /*!< Macronix memory standard       */
  EXTMEM_CUSTOM_STD_APMEM,        /*!< AP Memory standard             */
  EXTMEM_CUSTOM_STD_MACRONIX_RAM, /*!< Macronix RAM memory standard   */
  EXTMEM_CUSTOM_STD_HYPERBUS,     /*!< HyperBus memory standard (Only used for HyperRAM)      */
  EXTMEM_CUSTOM_STD_APMEM_16BITS  /*!< AP Memory 16-bit standard (Only available on XSPIM Port1)    */
} EXTMEM_CUSTOM_MemStdTypeDef;
  • Description: Selects the vendor/standard behavior used by the controller. It mainly impacts Octal-SPI DDR/DTR transfers (8-data-bit mode): data bit ordering and DQS usage, and may also affect command compatibility, timing, and special features.
    • Modes overview:
      • EXTMEM_CUSTOM_STD_MICRON: D0/D1 ordering in DTR 8-data-bit mode, regular-command protocol in 1/2/4/8-SPI modes, DQS polarity is inverted with respect to the memory clock.
      • EXTMEM_CUSTOM_STD_MACRONIX: D1/D0 ordering in DTR 8-data-bit mode, regular-command protocol in 1/2/4/8-SPI modes.
      • EXTMEM_CUSTOM_STD_APMEM: D0/D1 ordering in DTR 8-data-bit mode, regular-command protocol in 1/2/4/8-SPI modes, standard for AP Memory devices using a 8-bit data bus.
      • EXTMEM_CUSTOM_STD_MACRONIX_RAM: D1/D0 ordering in DTR 8-data-bit mode, regular-command protocol in 1/2/4/8-SPI modes, with dedicated address mapping (row/column-based) to fit Macronix RAM requirements.
      • EXTMEM_CUSTOM_STD_HYPERBUS: Protocol follows the HyperBus specification, supports memory mode and register mode (addressing register space). This standard is only used for HyperRAM.
      • EXTMEM_CUSTOM_STD_APMEM_16BITS: Standard for AP Memory devices using a 16-bit data bus (shift operation on the left from the address bit 10 done by the HW to fit the provider requirement).
    • Note:
      • EXTMEM_CUSTOM_STD_MICRON is the default value, ensures the selected standard matches the connected memory.
  • Where can I find this information?
    • Memory datasheet: Ordering information
    • Memory datasheet: General description
    • Memory datasheet: Manufacturer logo or part number prefix on the first page
  • When is this parameter needed?
    • When configuring device-specific features or ensuring compatibility with the driver.

3.1.3. MemSize

 /**
  * @brief Enumeration of supported memory sizes.
  */
typedef enum
{
  EXTMEM_CUSTOM_SIZE_16B,    /*!<  16 bits  (  2  Bytes = 2^( 0+1)) */
  EXTMEM_CUSTOM_SIZE_32B,    /*!<  32 bits  (  4  Bytes = 2^( 1+1)) */
  EXTMEM_CUSTOM_SIZE_64B,    /*!<  64 bits  (  8  Bytes = 2^( 2+1)) */
  EXTMEM_CUSTOM_SIZE_128B,   /*!< 128 bits  ( 16  Bytes = 2^( 3+1)) */
  EXTMEM_CUSTOM_SIZE_256B,   /*!< 256 bits  ( 32  Bytes = 2^( 4+1)) */
  EXTMEM_CUSTOM_SIZE_512B,   /*!< 512 bits  ( 64  Bytes = 2^( 5+1)) */
  EXTMEM_CUSTOM_SIZE_1KB,    /*!<   1 Kbits (128  Bytes = 2^( 6+1)) */
  EXTMEM_CUSTOM_SIZE_2KB,    /*!<   2 Kbits (256  Bytes = 2^( 7+1)) */
  EXTMEM_CUSTOM_SIZE_4KB,    /*!<   4 Kbits (512  Bytes = 2^( 8+1)) */
  EXTMEM_CUSTOM_SIZE_8KB,    /*!<   8 Kbits (  1 KBytes = 2^( 9+1)) */
  EXTMEM_CUSTOM_SIZE_16KB,   /*!<  16 Kbits (  2 KBytes = 2^(10+1)) */
  EXTMEM_CUSTOM_SIZE_32KB,   /*!<  32 Kbits (  4 KBytes = 2^(11+1)) */
  EXTMEM_CUSTOM_SIZE_64KB,   /*!<  64 Kbits (  8 KBytes = 2^(12+1)) */
  EXTMEM_CUSTOM_SIZE_128KB,  /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */
  EXTMEM_CUSTOM_SIZE_256KB,  /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */
  EXTMEM_CUSTOM_SIZE_512KB,  /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */
  EXTMEM_CUSTOM_SIZE_1MB,    /*!<   1 Mbits (128 KBytes = 2^(16+1)) */
  EXTMEM_CUSTOM_SIZE_2MB,    /*!<   2 Mbits (256 KBytes = 2^(17+1)) */
  EXTMEM_CUSTOM_SIZE_4MB,    /*!<   4 Mbits (512 KBytes = 2^(18+1)) */
  EXTMEM_CUSTOM_SIZE_8MB,    /*!<   8 Mbits (  1 MBytes = 2^(19+1)) */
  EXTMEM_CUSTOM_SIZE_16MB,   /*!<  16 Mbits (  2 MBytes = 2^(20+1)) */
  EXTMEM_CUSTOM_SIZE_32MB,   /*!<  32 Mbits (  4 MBytes = 2^(21+1)) */
  EXTMEM_CUSTOM_SIZE_64MB,   /*!<  64 Mbits (  8 MBytes = 2^(22+1)) */
  EXTMEM_CUSTOM_SIZE_128MB,  /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */
  EXTMEM_CUSTOM_SIZE_256MB,  /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */
  EXTMEM_CUSTOM_SIZE_512MB,  /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */
  EXTMEM_CUSTOM_SIZE_1GB,    /*!<   1 Gbits (128 MBytes = 2^(26+1)) */
  EXTMEM_CUSTOM_SIZE_2GB,    /*!<   2 Gbits (256 MBytes = 2^(27+1)) */
  EXTMEM_CUSTOM_SIZE_4GB,    /*!<   4 Gbits (512 MBytes = 2^(28+1)) */
  EXTMEM_CUSTOM_SIZE_8GB,    /*!<   8 Gbits (  1 GBytes = 2^(29+1)) */
  EXTMEM_CUSTOM_SIZE_16GB,   /*!<  16 Gbits (  2 GBytes = 2^(30+1)) */
  EXTMEM_CUSTOM_SIZE_32GB    /*!<  32 Gbits (  4 GBytes = 2^(31+1)) */
} EXTMEM_CUSTOM_MemSizeTypeDef;
  • Description: Defines the total storage capacity of the memory device, from bits to gigabits. Essential for addressing and memory mapping.
  • Where can I find this information?
    • Memory datasheet: Product overview
    • Memory datasheet: Memory organization table
    • Memory datasheet: Ordering information
  • When is this parameter needed?
    • Always

3.1.4. ResetMethod

 /**
  * @brief Enumeration of possible reset methods defined in the configuration file.
  */
typedef enum
{
  EXTMEM_CUSTOM_RESET_METHOD_UNDEFINED, /*!< Reset method is not used/defined in configuration file */
  EXTMEM_CUSTOM_RESET_METHOD_66_99,     /*!< Reset method using 66h and 99h instructions */
  EXTMEM_CUSTOM_RESET_METHOD_6699_9966, /*!< Reset method using 6699h and 9966h instructions */
  EXTMEM_CUSTOM_RESET_METHOD_6666_9999, /*!< Reset method using 6666h and 9999h instructions */
  EXTMEM_CUSTOM_RESET_METHOD_FF         /*!< Reset method using FFh instructions */
} EXTMEM_CUSTOM_ResetMethodTypeDef;
  • Description: Specifies the command sequence required to reset the memory device (e.g., 66h/99h, 6699h/9966h, FFh).
  • Where can I find this information?
    • Memory datasheet: Command set section
    • Memory datasheet: Reset operations
    • Memory datasheet: Initialization (instructions/commands chapter)
  • When is this parameter needed?
    • Always, except for HyperRAM (set to UNDEFINED).

3.1.5. SampleShiftCfg

 /**
  * @brief Enumeration of Sample Shift configurations.
  */
typedef enum
{
  EXTMEM_CUSTOM_SSHIFT_CFG_UNDEFINED,  /*!< Sample Shift setting not provided in configuration file */
  EXTMEM_CUSTOM_SSHIFT_CFG_NONE,       /*!< Sample Shift setting provided in configuration file, and to be set to None */
  EXTMEM_CUSTOM_SSHIFT_CFG_HALFCYCLE   /*!< Sample Shift setting provided in configuration file, and to be set to Half-cycle */
} EXTMEM_CUSTOM_SShiftCfgTypeDef;
  • Description: Configures the sample shift for data alignment (e.g., None, Half-cycle). Important for high-speed interfaces to ensure reliable data capture. This parameter is only necessary in STR mode and must be disabled/set to none when using DTR mode.
  • Where can I find this information?
    • Memory datasheet: Timing characteristics
    • Memory datasheet: Electrical characteristics
    • Memory datasheet: Interface timing diagrams (look for "Data Valid Window" or sample-shift guidance)
  • When is this parameter needed?
    • When configuring high-speed interfaces and when the memory datasheet recommends a sample shift (typically at high frequency in STR mode).

3.1.6. ResetDelay

  • Description: Specifies the required delay (milliseconds) after issuing a reset command before the device is ready for operation.
  • Where can I find this information?
    • Memory datasheet: AC characteristics
    • Memory datasheet: Reset timing
    • Memory datasheet: Initialization timing table
  • When is this parameter needed?
    • When the selected ResetMethod requires a wait time before the device is ready.
    • Set to 0 if no delay is required (set 0 for HyperRAM).

3.1.7. MemChipSelectHighTimeCycle

  • Description: Minimum time (number of cycles) the chip select (CS) signal must remain high between memory operations.
  • Conversion from time: If the datasheet specifies this as a minimum time t_ns (ns) and the interface clock is f_hz, use: N_cycles = (t_ns * f_hz / 1e9), rounded up to the next integer, so the generated CS-high time is not shorter than required.
  • Where can I find this information?
    • Memory datasheet: Timing diagrams
    • Memory datasheet: AC timing parameters (look for "tCSH", "tCSHI", chip-select high time, or similar)
  • When is this parameter needed?
    • Always

3.2. Startup configuration

                                   .StartupConfig.Frequency              /*!< Operating frequency in Hz*/ \
                                   .StartupConfig.CommandRead            /*!< Command to read data */ \
                                   .StartupConfig.CommandWrite           /*!< Command to write data */ \
                                   .StartupConfig.DummyCycleRead         /*!< Number of dummy cycles for read operations */ \
                                   .StartupConfig.DummyCycleWrite        /*!< Number of dummy cycles for write operations */ \
                                   .StartupConfig.DummyRegisterRead      /*!< Number of dummy cycles to read register */ \
                                   .StartupConfig.AccessMode             /*!< Access mode (e.g., 1S4D4D) */ \
                                   .StartupConfig.OptWriteAccessMode
                                   .StartupConfig.InstructionSize        /*!< Size of the instruction */ \
                                   .StartupConfig.AddressSize            /*!< Size of the address */ \
                                   .StartupConfig.DqsMode                /*!< Data strobe mode */ \

3.2.1. StartupConfig.Frequency

  • Description: The operating frequency (in Hz) at which the memory interface communicates with the external memory device.
  • Where can I find this information?
    • Memory datasheet: Features section
    • Memory datasheet: AC characteristics (look for "Operating Frequency" or "Clock Frequency")
    • MCU datasheet: XSPI/XSPIM maximum operating frequency and port limitations
  • When is this parameter needed?
    • When configuring the memory controller's clock settings to ensure reliable operation within the device’s supported frequency range.

3.2.2. StartupConfig.CommandRead

  • Description: The command opcode (8 or 16 bits depending on memory) used to initiate a read operation from the memory device.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Read operations
    • Memory datasheet: Instruction table (look for "Read Command" or "Read Data")
  • When is this parameter needed?
    • When setting up the read sequence in the driver to access memory contents (NOR Flash / PSRAM).
    • Not used for HyperRAM.


3.2.3. StartupConfig.CommandWrite

  • Description: The command opcode (8 or 16 bits depending on memory) used to initiate a write operation to the memory device.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Write operations
    • Memory datasheet: Instruction table (look for "Write Command" or "Page Program")
  • When is this parameter needed?
    • When setting up the write sequence in the driver to store data in memory (NOR Flash / PSRAM).
    • Not used for HyperRAM.


3.2.4. StartupConfig.DummyCycleRead

  • Description: The number of dummy clock cycles inserted during a read operation, typically required for high-speed reads.
  • Conversion from time: If the datasheet specifies a minimum read latency time t_ns (ns) for a given clock f_hz, use: N_cycles = (t_ns * f_hz / 1e9), rounded up to the next integer.
  • Where can I find this information?
    • Memory datasheet: Read operations
    • Memory datasheet: Timing diagrams
    • Memory datasheet: Command set (look for "Dummy Cycles" or "Read Latency")
  • When is this parameter needed?
    • When the selected read command requires dummy cycles (NOR Flash / PSRAM), set to 0 if none are required.
    • Not used for HyperRAM.

3.2.5. StartupConfig.DummyCycleWrite

  • Description: The number of dummy clock cycles inserted during a write operation, if required by the memory protocol.
  • Conversion from time: If the datasheet expresses a minimum write access latency as a time t_ns (ns) for a given clock f_hz, use: N_cycles = (t_ns * f_hz / 1e9), rounded up to the next integer.
  • Where can I find this information?
    • Memory datasheet: Write operations
    • Memory datasheet: Timing diagrams
    • Memory datasheet: Command set (look for "Dummy Cycles" in write instructions)
  • When is this parameter needed?
    • When the selected write command requires dummy cycles (NOR Flash / PSRAM), set to 0 if none are required.
    • Not used for HyperRAM.

3.2.6. StartupConfig.DummyRegisterRead

  • Description: The number of dummy clock cycles required when reading from a register (e.g., status or configuration register).
  • Conversion from time: If the datasheet provides a minimum register-read latency time t_ns (ns) for a given clock f_hz, use: N_cycles = (t_ns * f_hz / 1e9), rounded up to the next integer.
  • Where can I find this information?
    • Memory datasheet: Register read operations
    • Memory datasheet: Command set
    • Memory datasheet: Timing diagrams (look for "Register Read" or "Dummy Cycles")
  • When is this parameter needed?
    • When register reads require dummy cycles (NOR Flash / PSRAM), set to 0 if none are required.
    • Not used for HyperRAM.

3.2.7. StartupConfig.AccessMode

 /**
  * @brief Enumeration of combined access mode configurations.
  * @note  The naming convention is: [Instruction][Address][Data], where each field is
  *        represented by a number (bus width: 1, 4, 8, 16) and a letter (S = STR, D = DTR).
  *        For example, 1S_4D_4D means 1-line STR for instruction, 4-line DTR for address, 4-line DTR for data.
  */
typedef enum
{
  EXTMEM_CUSTOM_1S_1S_1S,  /*!< 1S instruction, 1S address, 1S data  */
  EXTMEM_CUSTOM_1S_1S_1D,  /*!< 1S instruction, 1S address, 1D data  */
  EXTMEM_CUSTOM_1S_1D_1S,  /*!< 1S instruction, 1D address, 1S data  */
  EXTMEM_CUSTOM_1S_1D_1D,  /*!< 1S instruction, 1D address, 1D data  */
  EXTMEM_CUSTOM_1D_1S_1S,  /*!< 1D instruction, 1S address, 1S data  */
  EXTMEM_CUSTOM_1D_1S_1D,  /*!< 1D instruction, 1S address, 1D data  */
  EXTMEM_CUSTOM_1D_1D_1S,  /*!< 1D instruction, 1D address, 1S data  */
  EXTMEM_CUSTOM_1D_1D_1D,  /*!< 1D instruction, 1D address, 1D data  */
  EXTMEM_CUSTOM_1S_1S_4S,  /*!< 1S instruction, 1S address, 4S data  */
  EXTMEM_CUSTOM_1S_1S_4D,  /*!< 1S instruction, 1S address, 4D data  */
  EXTMEM_CUSTOM_1S_1D_4S,  /*!< 1S instruction, 1D address, 4S data  */
  EXTMEM_CUSTOM_1S_1D_4D,  /*!< 1S instruction, 1D address, 4D data  */
  EXTMEM_CUSTOM_1S_4S_4S,  /*!< 1S instruction, 4S address, 4S data  */
  EXTMEM_CUSTOM_1S_4S_4D,  /*!< 1S instruction, 4S address, 4D data  */
  EXTMEM_CUSTOM_1S_4D_4S,  /*!< 1S instruction, 4D address, 4S data  */
  EXTMEM_CUSTOM_1S_4D_4D,  /*!< 1S instruction, 4D address, 4D data  */
  EXTMEM_CUSTOM_4S_4S_4S,  /*!< 4S instruction, 4S address, 4S data  */
  EXTMEM_CUSTOM_4S_4S_4D,  /*!< 4S instruction, 4S address, 4D data  */
  EXTMEM_CUSTOM_4S_4D_4S,  /*!< 4S instruction, 4D address, 4S data  */
  EXTMEM_CUSTOM_4S_4D_4D,  /*!< 4S instruction, 4D address, 4D data  */
  EXTMEM_CUSTOM_4D_4S_4S,  /*!< 4D instruction, 4S address, 4S data  */
  EXTMEM_CUSTOM_4D_4S_4D,  /*!< 4D instruction, 4S address, 4D data  */
  EXTMEM_CUSTOM_4D_4D_4S,  /*!< 4D instruction, 4D address, 4S data  */
  EXTMEM_CUSTOM_4D_4D_4D,  /*!< 4D instruction, 4D address, 4D data  */
  EXTMEM_CUSTOM_8S_8S_8S,  /*!< 8S instruction, 8S address, 8S data  */
  EXTMEM_CUSTOM_8S_8S_8D,  /*!< 8S instruction, 8S address, 8D data  */
  EXTMEM_CUSTOM_8S_8D_8S,  /*!< 8S instruction, 8D address, 8S data  */
  EXTMEM_CUSTOM_8S_8D_8D,  /*!< 8S instruction, 8D address, 8D data  */
  EXTMEM_CUSTOM_8D_8S_8S,  /*!< 8D instruction, 8S address, 8S data  */
  EXTMEM_CUSTOM_8D_8S_8D,  /*!< 8D instruction, 8S address, 8D data  */
  EXTMEM_CUSTOM_8D_8D_8S,  /*!< 8D instruction, 8D address, 8S data  */
  EXTMEM_CUSTOM_8D_8D_8D,  /*!< 8D instruction, 8D address, 8D data  */
  EXTMEM_CUSTOM_8S_8D_16D, /*!< 8S instruction, 8D address, 16D data */
  EXTMEM_CUSTOM_8D_8D_16D  /*!< 8D instruction, 8D address, 16D data */
} EXTMEM_CUSTOM_AccessModeTypeDef;
  • Description: Specifies the bus width and protocol for instruction, address, and data phases (e.g., 1S-4D-4D: 1 line STR for instruction, 4 lines DTR for address, 4 lines DTR for data).
    • S: STR (Single Transfer Rate)
    • D: DTR (Dual Transfer Rate)
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Read/write operation descriptions
    • Memory datasheet: Features (look for "I/O Modes" or "Bus Width")
    • MCU datasheet: XSPI/XSPIM supported bus widths and port limitations
  • When is this parameter needed?
    • When configuring the memory controller to match the memory’s supported access protocol.

3.2.8. StartupConfig.OptWriteAccessMode

 /**
  * @brief Enumeration of combined access mode configurations.
  * @note  The naming convention is: [Instruction][Address][Data], where each field is
  *        represented by a number (bus width: 1, 4, 8, 16) and a letter (S = STR, D = DTR).
  *        For example, 1S_4D_4D means 1-line STR for instruction, 4-line DTR for address, 4-line DTR for data.
  */
typedef enum
{
  EXTMEM_CUSTOM_1S_1S_1S,  /*!< 1S instruction, 1S address, 1S data  */
  EXTMEM_CUSTOM_1S_1S_1D,  /*!< 1S instruction, 1S address, 1D data  */
  EXTMEM_CUSTOM_1S_1D_1S,  /*!< 1S instruction, 1D address, 1S data  */
  EXTMEM_CUSTOM_1S_1D_1D,  /*!< 1S instruction, 1D address, 1D data  */
  EXTMEM_CUSTOM_1D_1S_1S,  /*!< 1D instruction, 1S address, 1S data  */
  EXTMEM_CUSTOM_1D_1S_1D,  /*!< 1D instruction, 1S address, 1D data  */
  EXTMEM_CUSTOM_1D_1D_1S,  /*!< 1D instruction, 1D address, 1S data  */
  EXTMEM_CUSTOM_1D_1D_1D,  /*!< 1D instruction, 1D address, 1D data  */
  EXTMEM_CUSTOM_1S_1S_4S,  /*!< 1S instruction, 1S address, 4S data  */
  EXTMEM_CUSTOM_1S_1S_4D,  /*!< 1S instruction, 1S address, 4D data  */
  EXTMEM_CUSTOM_1S_1D_4S,  /*!< 1S instruction, 1D address, 4S data  */
  EXTMEM_CUSTOM_1S_1D_4D,  /*!< 1S instruction, 1D address, 4D data  */
  EXTMEM_CUSTOM_1S_4S_4S,  /*!< 1S instruction, 4S address, 4S data  */
  EXTMEM_CUSTOM_1S_4S_4D,  /*!< 1S instruction, 4S address, 4D data  */
  EXTMEM_CUSTOM_1S_4D_4S,  /*!< 1S instruction, 4D address, 4S data  */
  EXTMEM_CUSTOM_1S_4D_4D,  /*!< 1S instruction, 4D address, 4D data  */
  EXTMEM_CUSTOM_4S_4S_4S,  /*!< 4S instruction, 4S address, 4S data  */
  EXTMEM_CUSTOM_4S_4S_4D,  /*!< 4S instruction, 4S address, 4D data  */
  EXTMEM_CUSTOM_4S_4D_4S,  /*!< 4S instruction, 4D address, 4S data  */
  EXTMEM_CUSTOM_4S_4D_4D,  /*!< 4S instruction, 4D address, 4D data  */
  EXTMEM_CUSTOM_4D_4S_4S,  /*!< 4D instruction, 4S address, 4S data  */
  EXTMEM_CUSTOM_4D_4S_4D,  /*!< 4D instruction, 4S address, 4D data  */
  EXTMEM_CUSTOM_4D_4D_4S,  /*!< 4D instruction, 4D address, 4S data  */
  EXTMEM_CUSTOM_4D_4D_4D,  /*!< 4D instruction, 4D address, 4D data  */
  EXTMEM_CUSTOM_8S_8S_8S,  /*!< 8S instruction, 8S address, 8S data  */
  EXTMEM_CUSTOM_8S_8S_8D,  /*!< 8S instruction, 8S address, 8D data  */
  EXTMEM_CUSTOM_8S_8D_8S,  /*!< 8S instruction, 8D address, 8S data  */
  EXTMEM_CUSTOM_8S_8D_8D,  /*!< 8S instruction, 8D address, 8D data  */
  EXTMEM_CUSTOM_8D_8S_8S,  /*!< 8D instruction, 8S address, 8S data  */
  EXTMEM_CUSTOM_8D_8S_8D,  /*!< 8D instruction, 8S address, 8D data  */
  EXTMEM_CUSTOM_8D_8D_8S,  /*!< 8D instruction, 8D address, 8S data  */
  EXTMEM_CUSTOM_8D_8D_8D,  /*!< 8D instruction, 8D address, 8D data  */
  EXTMEM_CUSTOM_8S_8D_16D, /*!< 8S instruction, 8D address, 16D data */
  EXTMEM_CUSTOM_8D_8D_16D  /*!< 8D instruction, 8D address, 16D data */
} EXTMEM_CUSTOM_AccessModeTypeDef;
  • Description: Specifies an optional or alternative access mode for write operations, if supported by the memory.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Write operation descriptions
    • Memory datasheet: Features (look for "Write Modes" or "Optional Modes")
    • MCU datasheet: XSPI/XSPIM supported bus widths and port limitations
  • When is this parameter needed?
    • When the memory supports multiple write protocols and the user wants to use an alternative mode.

3.2.9. StartupConfig.InstructionSize

 /**
  * @brief Enumeration of instruction bit sizes.
  */
typedef enum
{
  EXTMEM_CUSTOM_INSTRUCTION_8_BITS,  /*!< 8-bit instruction  */
  EXTMEM_CUSTOM_INSTRUCTION_16_BITS, /*!< 16-bit instruction */
  EXTMEM_CUSTOM_INSTRUCTION_24_BITS, /*!< 24-bit instruction */
  EXTMEM_CUSTOM_INSTRUCTION_32_BITS  /*!< 32-bit instruction */
} EXTMEM_CUSTOM_InstruSizeTypeDef;
  • Description: The size (in bits) of the instruction (command) field sent to the memory (e.g., 8, 16, 24, or 32 bits).
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Instruction format / opcode width
    • Memory datasheet: Timing Diagrams (look for "Instruction Size" or "Opcode Size")
  • When is this parameter needed?
    • When configuring the command phase for NOR Flash / PSRAM transactions.
    • Not used for HyperRAM.

3.2.10. StartupConfig.AddressSize

 /**
  * @brief Enumeration of address bit sizes.
  */
typedef enum
{
  EXTMEM_CUSTOM_ADDRESS_8_BITS,  /*!< 8-bit address  */
  EXTMEM_CUSTOM_ADDRESS_16_BITS, /*!< 16-bit address */
  EXTMEM_CUSTOM_ADDRESS_24_BITS, /*!< 24-bit address */
  EXTMEM_CUSTOM_ADDRESS_32_BITS  /*!< 32-bit address */
} EXTMEM_CUSTOM_AddrSizeTypeDef;
  • Description: The size (in bits) of the address field sent to the memory (e.g., 8, 16, 24, or 32 bits).
  • Where can I find this information?
    • Memory datasheet: Memory organization
    • Memory datasheet: Command set
    • Memory datasheet: Addressing section (look for "Address Size" or "Addressing Mode")
  • When is this parameter needed?
    • When configuring the address phase of memory transactions.

3.2.11. StartupConfig.DqsMode

/**
  * @brief Enumeration of DQS configurations.
  */
typedef enum
{
  EXTMEM_CUSTOM_DQS_DISABLE, /*!< DQS disabled */
  EXTMEM_CUSTOM_DQS_ENABLE   /*!< DQS enabled  */
} EXTMEM_CUSTOM_DqsModeTypeDef;
  • Description: Indicates whether the Data Strobe (DQS) signal is enabled or disabled. DQS is used for data alignment in high-speed memory interfaces.
  • Where can I find this information?
    • Memory datasheet: Features
    • Memory datasheet: Electrical characteristics and timing diagrams (look for "DQS" or "Data Strobe")
  • When is this parameter needed?
    • When using high-speed memory interfaces that support or require DQS for data latching.

3.3. Registers configuration

                                   .NbRegisterConfig                                                                    /*!< Common field for memory Chip select */ \
                                   .RegisterConfig[x].ConfigStepType                                                    /*!< Config step to read/write/read a register, send an instruction, execute optional configuration or call a user callback */ \
                                   .RegisterConfig[x].RWConfigStep.RegisterAddress                                      /*!< Address of the register */ \
                                   .RegisterConfig[x].RWConfigStep.CommandRegisterWrite                                 /*!< Command to write to a register */ \
                                   .RegisterConfig[x].RWConfigStep.CommandRegisterRead                                  /*!< Command to read from a register */ \
                                   .RegisterConfig[x].RWConfigStep.CommandRegisterReadAW                                /*!< Command to read from a register after write operation */ \
                                   .RegisterConfig[x].RWConfigStep.RegisterValue                                        /*!< Value of the register */ \
                                   .RegisterConfig[x].RWConfigStep.RegisterExpectedValue                                /*!< Expected value read back from the register */ \
                                   .RegisterConfig[x].RWConfigStep.RegisterMask                                         /*!< Mask for the register */ \
                                   .RegisterConfig[x].INSConfigStep.CommandRegisterWrite
                                   .RegisterConfig[x].INSConfigStep.CommandRegisterRead
                                   .RegisterConfig[x].INSConfigStep.Instruction
                                   .RegisterConfig[x].INSConfigStep.RegisterAddress
                                   .RegisterConfig[x].INSConfigStep.RegisterValue
                                   .RegisterConfig[x].CBConfigStep.Callback
                                   .RegisterConfig[x].CBConfigStep.UserCtx
                                   .RegisterConfig[x].CBConfigStep.Arg0
                                   .RegisterConfig[x].CBConfigStep.Arg1

3.3.1. NbRegisterConfig

  • Description: The number of register configuration steps or commands to be sent to the memory device during initialization or operation.
  • Where can I find this information?
    • Memory datasheet: Initialization sequence
    • Memory datasheet: Configuration register sections
    • Memory datasheet: Power-up sequence
  • When is this parameter needed?
    • When the memory device requires multiple register configurations for proper operation (e.g., setting modes, enabling features).

3.3.2. RegisterConfig[x].ConfigStepType

  • Description: Specifies the type of configuration step to execute. Depending on the selected value, the step can perform a register read/write sequence, a read-after-write verification, a pure read or write, a 16-bit register access (RR/WW), a 24-bit register access (RRR/WWW), an instruction-based operation, a switch to the optional memory configuration, or a user callback.
  • Where can I find this information?
    • Memory datasheet: Register map
    • Memory datasheet: Configuration register sections
    • Application Note: Number of steps used to configure the memory to get the final configuration
  • When is this parameter needed?
    • When defining the sequence of register operations required for device setup or mode switching.

Typical values are:

  • EXTMEM_CUSTOM_CFGSTEP_RW_REG[_ADDR]: read then write register
  • EXTMEM_CUSTOM_CFGSTEP_RWR_REG[_ADDR]: read, write, then read-back register
  • EXTMEM_CUSTOM_CFGSTEP_R_REG[_ADDR] / EXTMEM_CUSTOM_CFGSTEP_W_REG[_ADDR]: read-only or write-only register access
  • EXTMEM_CUSTOM_CFGSTEP_RR_REG[_ADDR] / EXTMEM_CUSTOM_CFGSTEP_WW_REG[_ADDR]: 16-bit register access
  • EXTMEM_CUSTOM_CFGSTEP_RRR_REG[_ADDR] / EXTMEM_CUSTOM_CFGSTEP_WWW_REG[_ADDR]: 24-bit register access
  • EXTMEM_CUSTOM_CFGSTEP_INST[_ADDR]: instruction-only step, with or without register address
  • EXTMEM_CUSTOM_CFGSTEP_INST_AND_READ[_ADDR]: send an instruction, then read back using the associated instruction-step fields
  • EXTMEM_CUSTOM_CFGSTEP_INST_WRITE[_ADDR]: send an instruction, then write using the associated instruction-step fields
  • EXTMEM_CUSTOM_CFGSTEP_EXEC_OPT_CFG: switch to the optional memory configuration
  • EXTMEM_CUSTOM_CFGSTEP_USER_CALLBACK: execute the user callback

3.3.3. RegisterConfig[x].RWConfigStep

/**
  * @brief Define the optional register configuration structure for RW register
  */
typedef struct
{
  uint32_t                         RegisterAddress;                               /*!< Address of the register */
  uint16_t                         CommandRegisterWrite;                          /*!< Command to write to a register */
  uint16_t                         CommandRegisterRead;                           /*!< Command to read from a register */
  uint16_t                         CommandRegisterReadAW;                         /*!< Command to read from a register after write operation (only used in RWR operation type) */
  uint32_t                         RegisterValue;                                 /*!< Value of the register */
  uint32_t                         RegisterExpectedValue;                         /*!< Value expected of the register. Used for comparison in RAW operation */
  uint32_t                         RegisterMask;                                  /*!< Mask for the register */
} RegAccess_TypeDef;

This structure is only used if ConfigStepType is using a direct register access operation (EXTMEM_CUSTOM_CFGSTEP_RW_REG[_ADDR], EXTMEM_CUSTOM_CFGSTEP_RWR_REG[_ADDR], EXTMEM_CUSTOM_CFGSTEP_R_REG[_ADDR] ...)

For 8-bit, 16-bit and 24-bit register accesses, the complete value and mask are stored in RegisterValue and RegisterMask:

  • 8-bit access: use bits [7:0]
  • 16-bit access: use bits [15:0]; bits [15:8] are transmitted first, then bits [7:0]
  • 24-bit access: use bits [23:0]; bits [23:16], then [15:8], then [7:0] are transmitted in that order
3.3.3.1. RegisterConfig[x].RWConfigStep.RegisterAddress
  • Description: The address of the register to be accessed (read or write).
  • Where can I find this information?
    • Memory datasheet: Register map
    • Memory datasheet: Command set
    • Memory datasheet: Device memory map
  • When is this parameter needed?
    • When performing direct register access operations.
3.3.3.2. RegisterConfig[x].RWConfigStep.CommandRegisterWrite
  • Description: The command opcode used to write data to the specified register.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Register write operations
    • Memory datasheet: Instruction table
  • When is this parameter needed?
    • When configuring or updating register values during initialization or runtime.
3.3.3.3. RegisterConfig[x].RWConfigStep.CommandRegisterRead
  • Description: The command opcode used to read data from the specified register.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Register read operations
    • Memory datasheet: Instruction table
  • When is this parameter needed?
    • When verifying register values or reading configuration/status information.
3.3.3.4. RegisterConfig[x].RWConfigStep.CommandRegisterReadAW
  • Description: The command opcode used to read a register immediately after a write operation (Read-After-Write), often for verification.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Register access sequences
    • Memory datasheet / application note: Read-after-write sequence description
  • When is this parameter needed?
    • When the protocol requires verification of a write by reading back the register value.
3.3.3.5. RegisterConfig[x].RWConfigStep.RegisterValue
  • Description: The value to be written to the register. For 8-bit, 16-bit and 24-bit configuration steps, it contains the complete encoded field value.
  • Where can I find this information?
    • Memory datasheet: Register map and bitfield descriptions
    • Memory datasheet / application note: Configuration register sequences
  • When is this parameter needed?
    • When the configuration step writes a register value.
3.3.3.6. RegisterConfig[x].RWConfigStep.RegisterExpectedValue
  • Description: The expected value read back from the register after a write operation. Used for comparison in RAW operations.
  • Where can I find this information?
    • Memory datasheet: Register map
    • Memory datasheet: Configuration register sections
  • When is this parameter needed?
    • When using a Read-After-Write (RAW) operation and the driver must verify the write by comparing the read-back value.
3.3.3.7. RegisterConfig[x].RWConfigStep.RegisterMask
  • Description: A bitmask used to isolate or modify specific bits within a register during read or write operations. For 16-bit and 24-bit accesses, it must be encoded with the same byte ordering as RegisterValue.
  • Where can I find this information?
    • Memory datasheet: Register map
    • Memory datasheet: Bit descriptions in register tables
  • When is this parameter needed?
    • When only certain bits of a register need to be changed or checked.

3.3.4. RegisterConfig[x].INSConfigStep

/**
  * @brief Define the optional register configuration structure for Additional Instruction sending
  */
typedef struct
{
  uint16_t                         CommandRegisterWrite;                          /*!< Command to write to a register */
  uint16_t                         CommandRegisterRead;                           /*!< Command to read from a register */
  uint16_t                         Instruction;                                   /*!< Instruction to be sent */
  uint16_t                         RegisterAddress;                               /*!< Address of the register */
  uint16_t                         RegisterValue;                                 /*!< Value of the register */
} Inst_TypeDef;

This structure is only used if ConfigStepType is using an instruction operation (EXTMEM_CUSTOM_CFGSTEP_INST[_ADDR], EXTMEM_CUSTOM_CFGSTEP_INST_AND_READ[_ADDR] or EXTMEM_CUSTOM_CFGSTEP_INST_WRITE[_ADDR])

3.3.4.1. RegisterConfig[x].INSConfigStep.CommandRegisterWrite
  • Description: The command opcode used to write to a register as part of an instruction-based configuration step.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Instruction table
    • Memory datasheet: Register write operations
  • When is this parameter needed?
    • When sending additional instructions for device configuration.
3.3.4.2. RegisterConfig[x].INSConfigStep.CommandRegisterRead
  • Description: The command opcode used to read from a register as part of an instruction-based configuration step.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Instruction table
    • Memory datasheet: Register read operations
  • When is this parameter needed?
    • When reading register values as part of a special instruction sequence.
3.3.4.3. RegisterConfig[x].INSConfigStep.Instruction
  • Description: The instruction code to be sent to the memory device, often used for special configuration or mode setting.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Special instructions section
  • When is this parameter needed?
    • When the device requires specific instructions for configuration or operation.
3.3.4.4. RegisterConfig[x].INSConfigStep.RegisterAddress
  • Description: The address of the register to be accessed in an instruction-based configuration step.
  • Where can I find this information?
    • Memory datasheet: Register map
    • Memory datasheet: Command set
    • Memory datasheet: Device memory map
  • When is this parameter needed?
    • When sending instructions that target specific registers.
3.3.4.5. RegisterConfig[x].INSConfigStep.RegisterValue
  • Description: The value to be written to the register in an instruction-based configuration step.
  • Where can I find this information?
    • Memory datasheet: Register map
    • Memory datasheet: Configuration register sections
  • When is this parameter needed?
    • When setting or updating register values as part of an instruction sequence.

3.3.5. RegisterConfig[x].CBConfigStep

/**
  * @brief Define the optional register configuration structure for User Callback.
  */
typedef struct
{
  EXTMEM_CUSTOM_UserCallbackTypeDef Callback;                                    /*!< User callback to execute */
  void                              *UserCtx;                                    /*!< Optional user context */
  uint32_t                          Arg0;                                        /*!< Optional argument 0 */
  uint32_t                          Arg1;                                        /*!< Optional argument 1 */
} UserCallback_TypeDef;

This structure is only used when ConfigStepType is EXTMEM_CUSTOM_CFGSTEP_USER_CALLBACK

The callback step allows the configuration sequence to execute user code from the memory object. The driver calls the weak function EXTMEM_DRIVER_CUSTOM_UserCallback(void *UserCtx, uint32_t UserArg0, uint32_t UserArg1), which can be overridden by the application.

3.3.5.1. RegisterConfig[x].CBConfigStep.Callback
  • Description: Callback function executed when the configuration step type is EXTMEM_CUSTOM_CFGSTEP_USER_CALLBACK.
  • Where can I find this information?
    • Not in memory or MCU datasheets: application code
    • Not in memory or MCU datasheets: board support or middleware integration code
  • When is this parameter needed?
    • When the configuration sequence needs custom processing that is not covered by the built-in register or instruction step types.
3.3.5.2. RegisterConfig[x].CBConfigStep.UserCtx
  • Description: Optional user context forwarded as-is to the callback.
  • Where can I find this information?
    • Not in memory or MCU datasheets: application design
    • Not in memory or MCU datasheets: board or memory integration context
  • When is this parameter needed?
    • When the callback needs access to a user-defined context or to the custom object itself.
3.3.5.3. RegisterConfig[x].CBConfigStep.Arg0
  • Description: First optional 32-bit argument passed to the callback.
  • Where can I find this information?
    • Not in memory or MCU datasheets: application design
  • When is this parameter needed?
    • When the callback needs an additional runtime parameter.
3.3.5.4. RegisterConfig[x].CBConfigStep.Arg1
  • Description: Second optional 32-bit argument passed to the callback.
  • Where can I find this information?
    • Not in memory or MCU datasheets: application design
  • When is this parameter needed?
    • When the callback needs a second additional runtime parameter.


3.4. Memory Type specific configuration

3.4.1. NOR Flash configuration parameters

                                   .NorFlashConfig.PageSize                                                             /*!< Page Size */ \
                                   .NorFlashConfig.SectorSize                                                           /*!< Sector Size */ \
                                   .NorFlashConfig.MaxSectorEraseTime                                                   /*!< Max time expected for completing a Sector Erase operation (in ms) */ \
                                   .NorFlashConfig.MaxChipEraseTime                                                     /*!< Max time expected for completing a Chip Erase operation (in ms) */ \
                                   .NorFlashConfig.Startup.Cmd_EraseSector                                              /*!< Command to erase a sector */ \
                                   .NorFlashConfig.Startup.Cmd_MassErase                                                /*!< Command to perform mass erase */ \
                                   .NorFlashConfig.Startup.Cmd_RDSR                                                     /*!< Command to read status register */ \
                                   .NorFlashConfig.Startup.Cmd_WE                                                       /*!< Command to enable write operations */ \
                                   .NorFlashConfig.Startup.MatchMask_WEL                                                /*!< Mask for write enable latch */ \
                                   .NorFlashConfig.Startup.MatchValue_WEL                                               /*!< Match Value for write enable latch */ \
                                   .NorFlashConfig.Startup.MatchMask_WIP                                                /*!< Mask for write in progress */ \
                                   .NorFlashConfig.Startup.MatchValue_WIP                                               /*!< Match Value for write in progress */ \
                                   .NorFlashConfig.OptionalConfigEnable                                                 /*!< Optional config for NorFlash is used */ \
                                   .NorFlashConfig.Optional.Cmd_EraseSector                                             /*!< Command to erase a sector */ \
                                   .NorFlashConfig.Optional.Cmd_MassErase                                               /*!< Command to perform mass erase */ \
                                   .NorFlashConfig.Optional.Cmd_RDSR                                                    /*!< Command to read status register in octal mode */ \
                                   .NorFlashConfig.Optional.Cmd_WE                                                      /*!< Command to enable write operations in octal mode */ \
                                   .NorFlashConfig.Optional.MatchMask_WEL                                               /*!< Mask for write enable latch */ \
                                   .NorFlashConfig.Optional.MatchValue_WEL                                              /*!< Match Value for write enable latch */ \
                                   .NorFlashConfig.Optional.MatchMask_WIP                                               /*!< Mask for write in progress */ \
                                   .NorFlashConfig.Optional.MatchValue_WIP                                              /*!< Match Value for write in progress */ \

/**
  * @brief Define the NOR configuration structure
  */
typedef struct
{
  uint32_t                         PageSize;                                      /*!< Page Size (Max write) */
  uint32_t                         SectorSize;                                    /*!< Sector Size in bytes  */
  uint32_t                         MaxSectorEraseTime;                            /*!< Max time expected for completing a Sector Erase operation (in ms) */
  uint32_t                         MaxChipEraseTime;                              /*!< Max time expected for completing a Chip Erase operation (in ms) */
  NorFlashBasConfigTypeDef         Startup;                                       /*!< Config use after boot */
  uint8_t                          OptionalConfigEnable;                          /*!< Optional NorFlash config activation if different from boot (RDSR/WE/Erase commands)  */
  NorFlashBasConfigTypeDef         Optional;                                      /*!< Config use after memory setup if different from boot (RDSR/WE/Erase commands) */
} NorFlashConfigTypeDef;
3.4.1.1. NorFlashConfig.PageSize
  • Description: The size (in bytes) of a programmable page, which is the smallest unit for a write operation.
  • Where can I find this information?
    • Memory datasheet: Features section
    • Memory datasheet: Memory organization table
  • When is this parameter needed?
    • Only when using a NOR Flash memory
3.4.1.2. NorFlashConfig.SectorSize
  • Description: The size (in bytes) of an erasable sector, which is the smallest unit for an erase operation.
  • Where can I find this information?
    • Memory datasheet: Features section
    • Memory datasheet: Memory organization table
    • Memory datasheet: Erase operations section
  • When is this parameter needed?
    • Only when using a NOR Flash memory
3.4.1.3. NorFlashConfig.MaxSectorEraseTime
  • Description: The maximum time (in ms) required to complete a sector erase operation.
  • Where can I find this information?
    • Memory datasheet: AC characteristics
    • Memory datasheet: Erase operations timing
    • Memory datasheet: Table labeled "Sector Erase Time" or equivalent
  • When is this parameter needed?
    • Only when using a NOR Flash memory
3.4.1.4. NorFlashConfig.MaxChipEraseTime
  • Description: The maximum time (in ms) required to complete a chip (mass) erase operation.
  • Where can I find this information?
    • Memory datasheet: AC characteristics
    • Memory datasheet: Erase operations timing
    • Memory datasheet: Table labeled "Chip Erase Time" or equivalent
  • When is this parameter needed?
    • Only when using a NOR Flash memory
3.4.1.5. Startup/Optional config
typedef struct
{
  EXTMEM_CUSTOM_SRAccessDetails    SRAccessDetails;                               /*!< Details about how to access SR for checking WIP, WEL bits */
  uint16_t                         Cmd_EraseSector;                               /*!< Command to erase a sector */
  uint16_t                         Cmd_MassErase;                                 /*!< Command to perform mass erase */
  uint16_t                         Cmd_RDSR;                                      /*!< Command to read status register */
  uint16_t                         Cmd_WE;                                        /*!< Command to enable write operations */
  uint8_t                          MatchMask_WEL;                                 /*!< Mask for write enable latch */
  uint8_t                          MatchValue_WEL;                                /*!< Match Value for write enable latch */
  uint8_t                          MatchMask_WIP;                                 /*!< Mask for write in progress */
  uint8_t                          MatchValue_WIP;                                /*!< Match Value for write in progress */
} NorFlashBasConfigTypeDef;
3.4.1.5.1. NorFlashConfig.Startup/Optional.SRAccessDetails
  • Description: Describes how the driver must access the status register that contains the WIP and WEL bits. Use this field when the memory requires an explicit register address for status-register reads.
  • Where can I find this information?
    • Memory datasheet: Status-register access description
    • Memory datasheet: Command set
    • Memory datasheet: Register map or protocol description for status polling
  • When is this parameter needed?
    • Only when the memory uses an addressed status-register access, otherwise keep it UNDEFINED.
    • Only when using a NOR Flash memory
3.4.1.5.2. NorFlashConfig.Startup/Optional.Cmd_EraseSector
  • Description: The command opcode used to erase a sector.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Erase operations
    • Memory datasheet: Instruction table
  • When is this parameter needed?
    • When issuing a sector erase command during normal operation or initialization.
    • Only when using a NOR Flash memory
3.4.1.5.3. NorFlashConfig.Startup/Optional.Cmd_MassErase
  • Description: The command opcode used to perform a chip (mass) erase.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Erase operations
    • Memory datasheet: Instruction table
  • When is this parameter needed?
    • When issuing a chip erase command to clear the entire memory.
    • Only when using a NOR Flash memory
3.4.1.5.4. NorFlashConfig.Startup/Optional.Cmd_RDSR
  • Description: The command opcode used to read the status register.
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Status-register section
    • Memory datasheet: Instruction table
  • When is this parameter needed?
    • When polling the status register to check for operation completion or device status.
    • Only when using a NOR Flash memory
3.4.1.5.5. NorFlashConfig.Startup/Optional.Cmd_WE
  • Description: The command opcode used to enable write operations (Write Enable).
  • Where can I find this information?
    • Memory datasheet: Command set
    • Memory datasheet: Write Enable/Disable section
    • Memory datasheet: Instruction table
  • When is this parameter needed?
    • Before any write or erase operation to set the write enable latch.
    • Only when using a NOR Flash memory
3.4.1.5.6. NorFlashConfig.Startup/Optional.MatchMask_WEL
  • Description: Bitmask used to isolate the Write Enable Latch (WEL) bit in the status register.
  • Where can I find this information?
    • Memory datasheet: Status-register section
    • Memory datasheet: Bit descriptions in register tables
  • When is this parameter needed?
    • When checking if the write enable latch is set before a write/erase operation.
    • Only when using a NOR Flash memory
3.4.1.5.7. NorFlashConfig.Startup/Optional.MatchValue_WEL
  • Description: The value to match against the WEL bit in the status register to confirm write enable status.
  • Where can I find this information?
    • Memory datasheet: Status-register section
    • Memory datasheet: Bit descriptions in register tables
  • When is this parameter needed?
    • When polling the status register to confirm write enable is active.
    • Only when using a NOR Flash memory
3.4.1.5.8. NorFlashConfig.Startup/Optional.MatchMask_WIP
  • Description: Bitmask used to isolate the Write In Progress (WIP) bit in the status register.
  • Where can I find this information?
    • Memory datasheet: Status-register section
    • Memory datasheet: Bit descriptions in register tables
  • When is this parameter needed?
    • When polling the status register to check if a write or erase operation is ongoing.
    • Only when using a NOR Flash memory
3.4.1.5.9. NorFlashConfig.Startup/Optional.MatchValue_WIP
  • Description: The value to match against the WIP bit in the status register to determine if the device is busy.
  • Where can I find this information?
    • Memory datasheet: Status-register section
    • Memory datasheet: Bit descriptions in register tables
  • When is this parameter needed?
    • When polling the status register to wait for operation completion.
    • Only when using a NOR Flash memory
3.4.1.6. NorFlashConfig.OptionalConfigEnable
  • Description: Indicates (true or false) if an optional NOR Flash configuration (different from startup) should be used after initialization.
  • Where can I find this information?
    • Memory datasheet / application note: Device configuration and mode-switching documentation
  • When is this parameter needed?
    • When the device requires a different configuration after boot or for specific operation modes.
    • Only when using a NOR Flash memory

3.4.2. PSRAM configuration parameters

                                   .PsramConfig.WrapSize
                                   .PsramConfig.CsBoundarySize
                                   .PsramConfig.Refresh
3.4.2.1. PsramConfig.WrapSize
  • Description: The wrap size defines the length (in bytes) of a burst or wrap access in PSRAM. It determines how many bytes are accessed in a single wrap or burst operation before the address wraps around to the start of the burst.
  • Where can I find this information?
    • Memory datasheet: Features section
    • Memory datasheet: Burst/Wrap mode section
    • Memory datasheet: Command set or timing diagrams (look for "Wrap Size", "Burst Length", or "Wrap Boundary")
  • When is this parameter needed?
    • Only when using a PSRAM memory


3.4.2.2. PsramConfig.CsBoundarySize
  • Description: The chip-select boundary size defines the address boundary at which the controller de-asserts chip select during accesses. It is used to match memories that require CS to toggle at specific burst or row boundaries.
  • Where can I find this information?
    • Memory datasheet: Memory organization section
    • Memory datasheet: Features section
    • Memory datasheet: Timing diagrams (look for "CS Boundary", "Burst Boundary", "Row Boundary", or "Page Boundary")
  • When is this parameter needed?
    • Only when using a PSRAM memory
3.4.2.3. PsramConfig.Refresh
  • Description: Refresh configuration value used by the controller for memories that require periodic refresh management.

Usually the memory has the "Self-managed" refresh feature meaning as long as the dummy cycles are properly set in the memory configuration

  • Conversion from time: If the refresh requirement is given as a minimum time t_ref_ns (ns), choose: N_cycles = (t_ref_ns * f_hz / 1e9), rounded up to the next integer.
  • Where can I find this information?
    • Memory datasheet: AC characteristics
    • Memory datasheet: Timing diagrams (look for "tRFH")
  • When is this parameter needed?
    • Only when using a PSRAM memory and when the controller requires an explicit refresh setting.

3.4.3. HyperRAM configuration parameters

                                   .HyperRamConfig.HyperbusConfig.RwRecoveryTimeCycle
                                   .HyperRamConfig.HyperbusConfig.AccessTimeCycle
                                   .HyperRamConfig.HyperbusConfig.WriteZeroLatency
                                   .HyperRamConfig.HyperbusConfig.LatencyMode
                                   .HyperRamConfig.RamConfig.WrapSize
                                   .HyperRamConfig.RamConfig.CsBoundarySize
                                   .HyperRamConfig.RamConfig.Refresh

This HyperBus section applies to HyperRAM only.

3.4.3.1. HyperRamConfig.HyperbusConfig.RwRecoveryTimeCycle
  • Description: The minimum number of clock cycles required between the end of a read or write operation and the start of the next read or write operation. This ensures proper timing and data integrity.
  • Conversion from time: If the datasheet specifies a minimum recovery time t_ns (ns), use: N_cycles = (t_ns * f_hz / 1e9), rounded up to the next integer.
  • Where can I find this information?
    • Memory datasheet: AC timing characteristics
    • Memory datasheet: Read/write recovery timing
    • Memory datasheet: Timing diagrams (look for "tRWREC" or read/write recovery time)
  • When is this parameter needed?
    • Only when using a HyperRAM memory


3.4.3.2. HyperRamConfig.HyperbusConfig.AccessTimeCycle
  • Description: The number of clock cycles from the assertion of chip select (CS#) to the availability of valid data (for reads) or the start of a write operation. It defines the access latency.
  • Conversion from time: If the datasheet specifies a minimum access time t_ns (ns), use: N_cycles = (t_ns * f_hz / 1e9), rounded up to the next integer.
  • Where can I find this information?
    • Memory datasheet: AC timing characteristics
    • Memory datasheet: Read/write access timing
    • Memory datasheet: Timing diagrams (look for "tACC" or access time)
  • When is this parameter needed?
    • Only when using a HyperRAM memory


3.4.3.3. HyperRamConfig.HyperbusConfig.WriteZeroLatency
  • Description: Indicates (true or false) whether zero-latency writes are supported/enabled. If enabled, write operations can start immediately without additional wait states.
  • Where can I find this information?
    • Memory datasheet: Features section
    • Memory datasheet: Write operation timing
    • Memory datasheet: HyperBus protocol description (look for "Zero Latency Write")
  • When is this parameter needed?
    • Only when using a HyperRAM memory


3.4.3.4. HyperRamConfig.HyperbusConfig.LatencyMode
  • Description: Selects the latency mode for memory access (e.g., fixed or variable latency). This affects how the controller handles wait states and data access timing.
  • Where can I find this information?
    • Memory datasheet: Features section
    • Memory datasheet: Latency configuration/timing
    • Memory datasheet: HyperBus protocol description (look for "Latency Mode", "Fixed Latency", or "Variable Latency")
  • When is this parameter needed?
    • Only when using a HyperRAM memory
3.4.3.5. HyperRamConfig.RamConfig.CsBoundarySize
  • Description: The chip-select boundary size defines the address boundary at which the controller de-asserts chip select during accesses. It is used when the HyperRAM device requires CS to toggle at specific burst or row boundaries.
  • Where can I find this information?
    • Memory datasheet: Memory organization section
    • Memory datasheet: Features section
    • Memory datasheet: Timing diagrams (look for "CS Boundary", "Row Boundary", or "Page Boundary")
  • When is this parameter needed?
    • Only when using a HyperRAM memory
3.4.3.6. HyperRamConfig.RamConfig.WrapSize
  • Description: The length (in bytes) of a burst or wrap access. Determines how many bytes are accessed in a single burst before the address wraps around.
  • Where can I find this information?
    • Memory datasheet: Features section
    • Memory datasheet: Burst/Wrap mode section
    • Memory datasheet: Timing diagrams (look for "Wrap Size" or "Burst Length")
  • When is this parameter needed?
    • Only when using a HyperRAM memory
3.4.3.7. HyperRamConfig.RamConfig.Refresh
  • Description: Refresh configuration value (in number of cycles) used by the controller for HyperRAM memories when an explicit refresh setting is required.

Usually the memory has the "Self-managed" refresh feature meaning as long as the dummycycles are properly set in the memory configuration

  • Conversion from time: If the refresh requirement is given as a minimum time t_ref_ns (ns), choose: N_cycles = (t_ref_ns * f_hz / 1e9), rounded up to the next integer
  • Where can I find this information?
    • Memory datasheet: AC characteristics
    • Memory datasheet: Configuration-register description
    • Memory datasheet: Timing diagrams (look for "tRFH")
  • When is this parameter needed?
    • Only when using a HyperRAM memory and when the controller requires an explicit refresh setting.


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